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With a November deadline for feature freeze fast approaching, GNU toolchain developers are now adding the last feature additions to GCC 9.0 (GNU Compiler Collection). Ahead of that deadline, AMD has released their first basic patch adding the "znver2" target and therefore Zen 2 support to GCC. While the patch uses the same cost tables and scheduler data as Znver1, it does feature three new instructions that will be available to AMD's next-gen CPUs which include; Cache Line Write Back (CLWB), Read Processor ID (RDPID), and Write Back and Do Not Invalidate Cache (WBNOINVD).
These three instructions are the only ones that have been found thus far by digging through the current code. Taking into account this is the first patch it can be considered a jumping off point, making sure that the GCC 9.1 stable update, which comes out in 2019, has support for Zen 2. Further optimizations and instructions may be implemented in the future. This is likely since AMD has yet to update the scheduler cost tables and by extension means they may not want to reveal everything about Zen 2 just yet. You could say AMD is for now playing it safe, at least until their 7nm EPYC 2 processors launch in 2019.
View at TechPowerUp Main Site
These three instructions are the only ones that have been found thus far by digging through the current code. Taking into account this is the first patch it can be considered a jumping off point, making sure that the GCC 9.1 stable update, which comes out in 2019, has support for Zen 2. Further optimizations and instructions may be implemented in the future. This is likely since AMD has yet to update the scheduler cost tables and by extension means they may not want to reveal everything about Zen 2 just yet. You could say AMD is for now playing it safe, at least until their 7nm EPYC 2 processors launch in 2019.
View at TechPowerUp Main Site