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TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.
This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.
In this TSMC and Broadcom CoWoS platform collaboration, Broadcom defined the complex top-die, interposer and HBM configuration while TSMC developed the robust manufacturing process to maximize yield and performance and meet the unique challenges of the 2X reticle size interposer. Through the experience of multiple generations of development of the CoWoS platform, TSMC innovated and developed a unique mask-stitching process enabling expansion beyond full reticle size, to bring this enhancement to volume production.
"Broadcom is happy to have collaborated with TSMC on advancing the CoWoS platform to address a host of design challenges at 7 nm and beyond," said Greg Dix, Vice President of Engineering for the ASIC Products Division at Broadcom. "Together, we are driving innovation with unprecedented compute, I/O and memory integration and paving the way for new and emerging applications including AI, Machine Learning, and 5G Networking."
"TSMC's ongoing R&D efforts have enabled us to double the sizeof the CoWoS interposer since this platform was first introduced in 2012, demonstrating our unwavering dedication to continuous innovation," said Dr. Douglas Yu, Vice President of Integrated Interconnect & Packaging in the R&D Organization of TSMC. "Our work with Broadcom on CoWoS is an excellent example of how our close collaboration with customers delivers even greater system-level HPC performance."
CoWoS is part of TSMC's portfolio of Wafer-Level System Integration (WLSI) solutions enabling system-level scaling both complementary to and beyond shrinking transistors. In addition to CoWoS, TSMC's innovative 3DIC technology platforms, such as Integrated Fan Out (InFO) and System on Integrated Chips (SoIC) enable innovation through chiplet partitioning and systems integration that achieves greater functionality and enhanced system performance.
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This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.
In this TSMC and Broadcom CoWoS platform collaboration, Broadcom defined the complex top-die, interposer and HBM configuration while TSMC developed the robust manufacturing process to maximize yield and performance and meet the unique challenges of the 2X reticle size interposer. Through the experience of multiple generations of development of the CoWoS platform, TSMC innovated and developed a unique mask-stitching process enabling expansion beyond full reticle size, to bring this enhancement to volume production.
"Broadcom is happy to have collaborated with TSMC on advancing the CoWoS platform to address a host of design challenges at 7 nm and beyond," said Greg Dix, Vice President of Engineering for the ASIC Products Division at Broadcom. "Together, we are driving innovation with unprecedented compute, I/O and memory integration and paving the way for new and emerging applications including AI, Machine Learning, and 5G Networking."
"TSMC's ongoing R&D efforts have enabled us to double the sizeof the CoWoS interposer since this platform was first introduced in 2012, demonstrating our unwavering dedication to continuous innovation," said Dr. Douglas Yu, Vice President of Integrated Interconnect & Packaging in the R&D Organization of TSMC. "Our work with Broadcom on CoWoS is an excellent example of how our close collaboration with customers delivers even greater system-level HPC performance."
CoWoS is part of TSMC's portfolio of Wafer-Level System Integration (WLSI) solutions enabling system-level scaling both complementary to and beyond shrinking transistors. In addition to CoWoS, TSMC's innovative 3DIC technology platforms, such as Integrated Fan Out (InFO) and System on Integrated Chips (SoIC) enable innovation through chiplet partitioning and systems integration that achieves greater functionality and enhanced system performance.
View at TechPowerUp Main Site