AMD EPYC "Genoa" Zen 4 Product Stack Leaked

[btarunr]

With its recent announcement of the Ryzen 7000 desktop processors, the action now shifts to the server, with AMD preparing a wide launch of its EPYC "Genoa" and "Bergamo" processors this year. Powered by the "Zen 4" microarchitecture, and contemporary I/O that includes PCI-Express Gen 5, CXL, and DDR5, these processors dial the CPU core-counts per socket up to 96 in case of "Genoa," and up to 128 in case of "Bergamo." The EPYC "Genoa" series represents the main trunk of the company's server processor lineup, with various internal configurations targeting specific use-cases.

The 96 cores are spread twelve 5 nm 8-core CCDs, each with a high-bandwidth Infinity Fabric path to the sIOD (server I/O die), which is very likely built on the 6 nm node. Lower core-count models can be built either by lowering the CCD count (ensuring more cores/CCD), or by reducing the number of cores/CCD and keeping the CCD-count constant, to yield more bandwidth/core. The leaked product-stack table below shows several of these sub-classes of "Genoa" and "Bergamo," classified by use-cases. The leaked slide also details the nomenclature AMD is using with its new processors. The leaked roadmap also mentions the upcoming "Genoa-X" processor for HPC and cloud-compute uses, which features the 3D Vertical Cache technology.



View at TechPowerUp Main Site | Source

 

[john_]

This is where AMD is focusing. On EPYC and Instinct. They don't care about putting a low price on the new Ryzen chips, or the upcoming Radeon GPUs. EPYC and Instinct. That's where the money is, and we can see this by looking how they try to create products for all segments. The new AMD is nothing like the old one having one product to do everything.

 

[springs113]

This is where AMD is focusing. On EPYC and Instinct. They don't care about putting a low price on the new Ryzen chips, or the upcoming Radeon GPUs. EPYC and Instinct. That's where the money is, and we can see this by looking how they try to create products for all segments. The new AMD is nothing like the old one having one product to do everything.

Actually, the new AMD designed a product that can be used in every segment. That is the true purpose of these Chiplet designs. Same r&d used basically for every cpu sector. There's more to this but that's just the gist of things.

 

[Crackong]

The new AMD is nothing like the old one having one product to do everything.

The CCD is the one product to do everything.
It is really the same concept.

 

[R0H1T]

They don't care about putting a low price on the new Ryzen chips, or the upcoming Radeon GPUs. EPYC and Instinct. That's where the money is, and we can see this by looking how they try to create products for all segments. The new AMD is nothing like the old one having one product to do everything.

That's generally true for AMD these days but you can also be sure that you'll get great deals on Ryzen over time ~ better than Intel IMO. For a new launch Intel seems to be ironically slightly better VFM, the same company that didn't reduce their CPU prices for what nearly ~1.5 decades!

 

[Jimmy_]

AMD is getting freaking MAD these days

 

[john_]

Actually, the new AMD designed a product that can be used in every segment. That is the true purpose of these Chiplet designs. Same r&d used basically for every cpu sector. There's more to this but that's just the gist of things.

The CCD is the one product to do everything.
It is really the same concept.

The idea is the same, but now we have two different types of Cores/CCDs, if I am not mistaken, one for Genoa and one for Bergamo, plus the option of the extra cache. It's not exactly one CCD for everything.

 

[R0H1T]

Yes Bergamo is slightly more interesting with 16c per CCD.

 

[mb194dc]

Server applications can actually use the extra cores and threads available. Much more marginal for desktop users, 3D versions of chips with 6 or 8 cores max probably makes sense for nearly all users.

Problem with servers is data centers move at glacial pace to change in my experience, especially new platforms etc.

 

[DeathtoGnomes]

so according to the core count chart 8 is 256 cores and 9 would be 512 cores, but I hate math.,..

 

[Crackong]

The idea is the same, but now we have two different types of Cores/CCDs, if I am not mistaken, one for Genoa and one for Bergamo, plus the option of the extra cache. It's not exactly one CCD for everything.

The Zen4c cores are exactly the same ISA as the regular Zen4, just reduced cache size.

It is not the same concept as P/E cores of Intel which has different ISA and causing compatibility issues.

 

[Punkenjoy]

The Zen4c cores are exactly the same ISA as the regular Zen4, just reduced cache size.

It is not the same concept as P/E cores of Intel which has different ISA and causing compatibility issues.

Stamping a bunch of E cores to ADL was Intel quick response to Zen dual ccd cpu. I can't believe they won't solve that in the future. Altough Intel always used ISA to segment their products, when SSE launched, it was just on high end, same thing with MMX.

i can't see them not adding AVX512 to their e-cores but we will see

 

[ARF]

This is where AMD is focusing. On EPYC and Instinct. They don't care about putting a low price on the new Ryzen chips, or the upcoming Radeon GPUs. EPYC and Instinct. That's where the money is, and we can see this by looking how they try to create products for all segments. The new AMD is nothing like the old one having one product to do everything.

They will be forced to, after the strong competitive pressure from the new 13th gen Core i-something line.
And the declining sales.

 

[Crackong]

Stamping a bunch of E cores to ADL was Intel quick response to Zen dual ccd cpu. I can't believe they won't solve that in the future. Altough Intel always used ISA to segment their products, when SSE launched, it was just on high end, same thing with MMX.

i can't see them not adding AVX512 to their e-cores but we will see

Hopefully Intel could solve that when they introduce their own chiplet design.
However based on the current situation of Sapphire Rapids, their multi chiplet design isn't going too well..

 

[ARF]

Hopefully Intel could solve that when they introduce their own chiplet design.
However based on the current situation of Sapphire Rapids, their multi chiplet design isn't going too well..

Wasn't intel blaming AMD for using "the glue"?
It's more like a strategy decision rather than an engineering or a design challenge.

The chiplet approach is the best for high core count servers, because it greatly improves the core per socket density.

 

[jesdals]

Yes Bergamo is slightly more interesting with 16c per CCD.

Has 16 cores been confirmed on Bergamo?

 

[Punkenjoy]

Hopefully Intel could solve that when they introduce their own chiplet design.
However based on the current situation of Sapphire Rapids, their multi chiplet design isn't going too well..

The issue with Sapphire rapids could be extrapoled to the whole Intel, Instead of trying to baby step improvement quickly, they want to do the big thing from day one and they face hundreds of issues that delay their product.

They have huge resource so they can overtime fix them but it slow them down quite a lot. The worst example of that is Ponte Vecchio that is just an absurb manufacturing nightmare. Intel can't stand not being the top and it make them over ambitious. Same thing with their foundry nodes. Their 10mn now renamed Intel 7 is very good, but it was such a big step from 14nm that they had huge issue to figure out all the problem.

 

[R0H1T]

i can't see them not adding AVX512 to their e-cores but we will see

They won't be adding AVX512 there, it wouldn't make them "E core" anymore.

Has 16 cores been confirmed on Bergamo?

Not really but most rumors from various reliable or BS sources all seem to say the same thing ~ 16c per CCD & 128c for the largest server chip.

 

[mashie]

That 9474F is quite a beast. Will be interesting to see how much they are on the second hand market in 4 years.

 

[Patriot]

Has 16 cores been confirmed on Bergamo?

Papermaster did say 2x core density on Zen4c, idk if it is confirmed but it is quite likely.

 

[Punkenjoy]

They won't be adding AVX512 there, it wouldn't make them "E core" anymore.


Not really but most rumors from various reliable or BS sources all seem to say the same thing ~ 16c per CCD & 128c for the largest server chip.

It's not much the lack of AVX512 that make them E-cores, it's the much smaller front end and way less execution units among other thing. They are lighter in all the day. They could support the AVX 512 ISA but not at the same speed than the main cores like it's certainly the case for almost all other instruction.

 

[john_]

Wasn't intel blaming AMD for using "the glue"?

Intel used glue to make it's first dual core processors and latter it's first quad core processors and that was a great idea back then. AMD lost time and money to build it's first native quad core, only to eat a TLB bug in the face that could not be fixed by software(without sacrificing significant performance) and the end result didn't really justified the effort. I think the gains where like low single digit performance advantage that couldn't cover the gap with Intel's Core 2 Duo and Core 2 Quad CPUs.

Glue is great at most times, at least for the last 15-20 years, no matter what the marketing departments of the competing companies say.

 

[Wirko]

It's not much the lack of AVX512 that make them E-cores, it's the much smaller front end and way less execution units among other thing. They are lighter in all the day. They could support the AVX 512 ISA but not at the same speed than the main cores like it's certainly the case for almost all other instruction.

The execution engine is scaringly big actually, and the front end seems quite powerful too.

Intel's Gracemont Small Core Eclipses Last-Gen Big Core Performance

Intel's Gracemont small core eclipses last-generation Skylake big core performance and energy efficiency

fuse.wikichip.org

For AVX512, Intel could resort to emulation in the hardware, but there's also a possibility of software emulation. Not that it could achieve usable performance but it could keep a thread from crashing if it gets assigned, by mistake, to an E-core.

Server applications can actually use the extra cores and threads available. Much more marginal for desktop users, 3D versions of chips with 6 or 8 cores max probably makes sense for nearly all users.

I'd say it's a bit more complex - Bergamo will hit a different point in the performance-power-area curve, and area is tied to both the price and the density. We'll see if Bergamo will be marketed as an universal processor or intended for specific use cases only (and it may not even have AVX512 if those use cases don't need it).

Problem with servers is data centers move at glacial pace to change in my experience, especially new platforms etc.

We the desktop users are beta testers for server technology. It's not the other way around (and that's good). The 3D V-cache is just the latest example of that.

Hopefully Intel could solve that when they introduce their own chiplet design.
However based on the current situation of Sapphire Rapids, their multi chiplet design isn't going too well..

I hope we'll know more details some day (much later, that's for sure). Is it the multi chiplet design that doesn't want to work as intended, or those pesky universities that find and report new vulnerabilites at regular intervals so you can never be done with the new design, or both, or something else? Also, why is there no leaks, no news, nothing at all, about single chiplet workstation Xeons with SPR inside? I'm very sure Intel is hard at work developing those, but the design may be collapsing faster than it's being built.

 

[Minus Infinity]

128 4c Core Epyc Bergamo, but we get 256 5c core Epyc Bergamo with Turin and will Sapphire Rapids even be shipping with its 56 cores by then LOL

Intel is on a hiding to nothing in this space. They should focus on HEDT. Sapphire Rapids for work stations before AMD gets Zen 4 Threadripper out.

 

[Crackong]

why is there no leaks, no news, nothing at all, about single chiplet workstation Xeons with SPR inside? I'm very sure Intel is hard at work developing those, but the design may be collapsing faster than it's being built.

Umm..
I think we all know where all the Intel 'Leaks' came from.
So I am not surprised not seeing 'Leaks' for a product currently at 'something hit the fan' state.