ASUS IoT Announces Tinker V—Tinkerboard Based on RISC-V

[btarunr]

ASUS IoT, the global AIoT solution provider, today announced the all-new Tinker V—a versatile single-board computer (SBC) powered by a 64-bit RISC-V-based processor, which supports both Linux Debian and Yocto operating systems. Tinker V packs features rich connectivity into a compact Pico-ITX form factor, and pairs assured longevity with reliable support, making it the ideal choice for diverse IoT and gateway applications.

The RISC-V processor in Tinker V employs the open-source Instruction Set Architecture (ISA), based on Reduced Instruction Set (RISC) principles. Compared with traditional x86 and Arm platforms, the defining benefit of RISC-V is that ISA is open source. Both individual developers and enterprises can change, optimize and deploy freely based on the RISC-V architecture—bypassing licensing and copyright fees.



The launch of Tinker V, based on RISC-V, represents ASUS IoT's ongoing commitment to accelerating IoT technologies, providing convenient and efficient environments for people everywhere.

Ideal for industrial IoT applications
The all-new Tinker V SBC is specially designed to run Linux Debian and Yocto. Featuring an ultra-compact size, it provides impressive power, comprehensive functionality and rich connectivity—making it the perfect choice for a diverse range of industrial IoT applications.

Specially, Tinker V is equipped with a Renesas RZ/Five MPU, which incorporates the RISC-V AndesCore AX45MP single-core supporting 1.0 GHz operating frequencies. It is also engineered with a broad spread of peripheral connectors for industrial use, including GPIO, micro-USB, dual gigabit Ethernet, a pair of CAN bus interfaces and two RS232 COM ports. It also benefits from 1 GB of built-in RAM and an optional 16 GB eMMC, while supporting a wide range of operating temperatures from as low as -20°C to as high as 60°C.

Strong collaboration fosters the fast-growing RISC-V ecosystem
Commenting on the launch of Tinker V, Shigeki Kato, Vice President of Renesas' Enterprise Infrastructure Business Division said: "We are thrilled to collaborate with ASUS and witness how our general-purpose RZ/Five MPU can contribute to the expansion of RISC-V in IoT systems. ASUS has been instrumental in integrating our device in the Tinker V SBC and we look forward to introducing more comprehensive RISC-V-based MPU solutions to our customers through our collaboration."

Dr. Charlie Su, President and CTO of Andes Technology, added: "Andes has collaborated with ASUS IoT for the exciting Tinker V product. This powerful single-board computer employs the Andes AX45MP, and I look forward to seeing more devices from innovators in the global industrial market embedded with Andes' advanced RISC-V processor families."

With the purchase of Tinker V, customers receive the assurance of at least five years of support from ASUS IoT, and dedicated on-site technical support is available to shorten customer development cycles and accelerate application deployment.

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[Denver]

Risc V has a serious problem which is the disparity between each design, it should have a universal base of instructions or something like that to ensure software compatibility.

 

[ncrs]

Risc V has a serious problem which is the disparity between each design, it should have a universal base of instructions or something like that to ensure software compatibility.

That's exactly what RISC-V has - there is a base instruction specification and many extensions.
The more important problem is that an ISA is just a relatively small part of a SoC. Everything around the CPU cores is not standardized, including the boot process. This is the same problem that ARM has. I am not sure it can really be solved. There is a UEFI specification for RISC-V, but all depends on the SoC and the designers of a particular solution. Ideally everyone would agree on a specific way of designing or at least booting SBCs, but it's doubtful to happen.