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Cadence Design Systems, Inc. today announced that it has collaborated with TSMC to optimize the Cadence Virtuoso platform for the 79 GHz mmWave design reference flow on TSMC's N16 process. With this latest development in Cadence and TSMC's long history of collaboration, joint customers now have access to a complete 79 GHz mmWave design reference flow on the N16 process for developing optimized, highly reliable, next-generation RFIC designs for use in radar, 5G and other wireless applications for the mobile, automotive, healthcare and aerospace markets. Customers have already started using the corresponding TSMC PDKs for RFIC design work.
The Cadence RFIC solution that supports TSMC's N16 process technology features automation capabilities to help customers spend less time integrating critical RF functionality into their designs. The solution supports all aspects of RF design, including passive device modeling, assisted layout automation, block-level optimization and EM signoff simulations.
The TSMC N16 79 GHz mmWave design reference flow incorporates an efficient methodology that lets engineers achieve their performance, power efficiency and reliability design goals. Customers can benefit from Cadence's tightly integrated Virtuoso ADE Suite and Spectre X Simulator with RF Option for managing corner simulations, design centering and identifying true worst-case corners. Furthermore, the Virtuoso Layout Suite for RF layout automation includes expedited placement and routing with in-design design rule check (DRC) capabilities.
Additionally, the TSMC N16 79 GHz mmWave design reference flow supports high-capacity electromagnetic (EM) model generation, leveraging the Cadence EMX Planar 3D Solver, which is essential for RF circuits. The Virtuoso platform tightly integrates with the EMX Planar 3D Solver and Cadence Quantus Parasitic Extraction to enable layered extraction of coupling effects, ensuring full-design EM parasitic signoff. This tight integration allows seamless back-annotation of S-parameter models into a golden IC schematic or a Quantus SmartView with post-layout parasitics. The flow demonstrates EM extraction using the Virtuoso EM assistant and stitching of the S-parameter model into the schematic for simulation and verification using the Virtuoso ADE Suite.
"Through our ongoing work with Cadence, we are empowering joint customers with the most advanced RF design tools and process technologies to bring innovative RFICs to market," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "The 79 GHz mmWave design reference flow on TSMC's N16 process makes it easier for our customers to quickly apply Cadence and TSMC innovations to their IC designs, and we can't wait to see the differentiated RFIC products they can create with the flow."
"Our strategic collaboration with TSMC provides a shared understanding of the real-world design challenges our customers face," said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. "This allows Cadence and TSMC to create intuitive solutions that automate high-frequency RFIC design so our customers can focus on creating new, value-added capabilities that differentiate their RFICs from the competition."
The Cadence RFIC solution supports the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence.
View at TechPowerUp Main Site
The Cadence RFIC solution that supports TSMC's N16 process technology features automation capabilities to help customers spend less time integrating critical RF functionality into their designs. The solution supports all aspects of RF design, including passive device modeling, assisted layout automation, block-level optimization and EM signoff simulations.
The TSMC N16 79 GHz mmWave design reference flow incorporates an efficient methodology that lets engineers achieve their performance, power efficiency and reliability design goals. Customers can benefit from Cadence's tightly integrated Virtuoso ADE Suite and Spectre X Simulator with RF Option for managing corner simulations, design centering and identifying true worst-case corners. Furthermore, the Virtuoso Layout Suite for RF layout automation includes expedited placement and routing with in-design design rule check (DRC) capabilities.
Additionally, the TSMC N16 79 GHz mmWave design reference flow supports high-capacity electromagnetic (EM) model generation, leveraging the Cadence EMX Planar 3D Solver, which is essential for RF circuits. The Virtuoso platform tightly integrates with the EMX Planar 3D Solver and Cadence Quantus Parasitic Extraction to enable layered extraction of coupling effects, ensuring full-design EM parasitic signoff. This tight integration allows seamless back-annotation of S-parameter models into a golden IC schematic or a Quantus SmartView with post-layout parasitics. The flow demonstrates EM extraction using the Virtuoso EM assistant and stitching of the S-parameter model into the schematic for simulation and verification using the Virtuoso ADE Suite.
"Through our ongoing work with Cadence, we are empowering joint customers with the most advanced RF design tools and process technologies to bring innovative RFICs to market," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "The 79 GHz mmWave design reference flow on TSMC's N16 process makes it easier for our customers to quickly apply Cadence and TSMC innovations to their IC designs, and we can't wait to see the differentiated RFIC products they can create with the flow."
"Our strategic collaboration with TSMC provides a shared understanding of the real-world design challenges our customers face," said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. "This allows Cadence and TSMC to create intuitive solutions that automate high-frequency RFIC design so our customers can focus on creating new, value-added capabilities that differentiate their RFICs from the competition."
The Cadence RFIC solution supports the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence.
View at TechPowerUp Main Site