- Joined
- Aug 19, 2017
- Messages
- 2,582 (0.97/day)
At VLSI Symposium 2023, scheduled to take place between June 11-16, Intel is set to demonstrate its PowerVia technology working efficiently on an E-Core chip built using the Intel 4 node. Conventional chips have power and signal interconnects distributed across multiple metal layers. PowerVia, on the other hand, dedicates specific layers for power delivery, effectively separating them from the signal routing layers. This approach allows for vertical power delivery through a set of power-specific Through-Silicon Vias (TSVs) or PowerVias, which are essentially vertical connections between the top and bottom surfaces of the chip. By delivering power directly from the backside of the chip, PowerVia reduces power supply noise and resistive losses, optimizing power distribution and improving overall energy efficiency. PowerVia is set to make a debut in 2024 with Intel 20A node.
For VLSI Symposium 2023 talk, the company has prepared a paper that highlights a design made using Intel 4 technology and implements E-Cores only in a test chip. The document states: "PowerVia Technology is a novel innovation to extend Process Scaling by having Power Delivery on the backside. This paper presents the pre and post silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of greater than 90 percent in large areas of the core while showing greater than 5 percent frequency benefit in silicon due reduced IR drop. Successful Post silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristics of the PowerVia testchip is inline with higher power densities expected from logic scaling."
Not only does PowerVia provide better frequency and reduced IR drop, but thermal management is a significant benefit as well. As logic scaling continues, more transistors are packed in a smaller space, increasing the thermal density. PowerVias should allow that to be a smaller problem and help heat escape more efficiently. Even though PowerVia is scheduled for the Intel 20A node, the company implemented it for Intel 4 node to learn and present how it works and how it is implemented to Intel Foundry Service (IFS) customers.
View at TechPowerUp Main Site | Source
For VLSI Symposium 2023 talk, the company has prepared a paper that highlights a design made using Intel 4 technology and implements E-Cores only in a test chip. The document states: "PowerVia Technology is a novel innovation to extend Process Scaling by having Power Delivery on the backside. This paper presents the pre and post silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of greater than 90 percent in large areas of the core while showing greater than 5 percent frequency benefit in silicon due reduced IR drop. Successful Post silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristics of the PowerVia testchip is inline with higher power densities expected from logic scaling."
Not only does PowerVia provide better frequency and reduced IR drop, but thermal management is a significant benefit as well. As logic scaling continues, more transistors are packed in a smaller space, increasing the thermal density. PowerVias should allow that to be a smaller problem and help heat escape more efficiently. Even though PowerVia is scheduled for the Intel 20A node, the company implemented it for Intel 4 node to learn and present how it works and how it is implemented to Intel Foundry Service (IFS) customers.
View at TechPowerUp Main Site | Source
