Intel Launches Agilex 7 FPGAs with R-Tile, First FPGA with PCIe 5.0 and CXL Capabilities

[btarunr]

Intel's Programmable Solutions Group today announced that the Intel Agilex 7 with the R-Tile chiplet is shipping production-qualified devices in volume - bringing customers the first FPGA with PCIe 5.0 and CXL capabilities and the only FPGA with hard intellectual property (IP) supporting these interfaces. "Customers are demanding cutting-edge technology that offers the scalability and customization needed to not only efficiently manage current workloads, but also pivot capabilities and functions as their needs evolve. Our Agilex products offer the programmable innovation with the speed, power and capabilities our customers need while providing flexibility and resilience for the future. For example, customers are leveraging R-Tile, with PCIe Gen 5 and CXL, to accelerate software and data analytics, cutting the processing time from hours to minutes," said Shannon Poulin, Intel corporate vice president and general manager of the Programmable Solutions Group.

Faced with time, budget and power constraints, organizations across industries including data center, telecommunications and financial services, turn to FPGAs as flexible, programmable and efficient solutions. Using Agilex 7 with R-Tile, customers can seamlessly connect their FPGAs with processors, such as 4th Gen Intel Xeon Scalable processors, with the highest bandwidth processor interfaces to accelerate targeted data center and high performance computing (HPC) workloads. Agilex 7's configurable and scalable architecture enables customers to quickly deploy customized technology - at scale with hardware speeds based on their specific needs - to reduce overall design costs and development processes and to expedite execution to achieve optimal data center performance.



How It Works: Agilex 7 FPGAs with the R-Tile chiplet deliver leading technology capabilities with 2-times faster PCIe 5.0 bandwidth as well as 4-times higher CXL bandwidth per port when compared to other competitive FPGA products. According to a white paper from Meta and the University of Michigan, adding FPGAs with CXL memory to 4th Gen Xeon-based servers while using transparent page placement's (TPP) efficient page placement improves Linux performance by up to 18%. Additionally, UnifabriX demonstrated its CXL-enabled Smart Memory Node on multiple performance benchmarks, with one showing a 28% increase in the HPCG (high-performance conjugate gradient) benchmark score while utilizing 2-times more 4th Gen Xeon cores for HPC workloads.

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[bonehead123]

Foget all that techno-babble, just make it smaller, faster, cooler, and cheaper already, then we'll have somethin to talk about, hehehe

 

[persondb]

Would be nice if they released an affordable(for hobbyist) version of Agilex. The devkits from Terasic cost way too much, except the old cyclone ones.

 

[LabRat 891]

I was just having 'bathroom thoughts' on the fact that both AMD and Intel own FPGA firms, yet neither has implemented an FPGA-section in their silicon (AFAIK).
Especially, with Intel looking at 'trimming the fat' off X86, a small FPGA in-silicon (seems like it) could be handy for running legacy code in real hardware.
(Or 'offering for sale/subscription' tiered hardware acceleration. knowing Intel...)

 

[alphaLONE]

I was just having 'bathroom thoughts' on the fact that both AMD and Intel own FPGA firms, yet neither has implemented an FPGA-section in their silicon (AFAIK).
Especially, with Intel looking at 'trimming the fat' off X86, a small FPGA in-silicon (seems like it) could be handy for running legacy code in real hardware.
(Or 'offering for sale/subscription' tiered hardware acceleration. knowing Intel...)

But AMD does that already. They've got XDNA in their new 7040 series APUs. And Intel's got several server chips with FPGA that go a long way back (from Stellarton Atoms to SPR with their little CPLD or FPGA on the package, without forgetting the Xeon Gold 6138P).

 

[trsttte]

Would be nice if they released an affordable(for hobbyist) version of Agilex. The devkits from Terasic cost way too much, except the old cyclone ones.

I just saw this tiny thing for 25$

$25 Sipeed Tang Nano 20K FPGA board can simulate a RISC-V core, run Linux, retro games - CNX Software

The Sipeed Tang Nano 20K is a low-cost FPGA development board based on Gowin GW2AR-18 FPGA with 20,736 logic cells and 64Mbit RAM, which coupled with

www.cnx-software.com

Not a lot of gates but plenty enough to get your feet wet

 

[Minus Infinity]

I was just having 'bathroom thoughts' on the fact that both AMD and Intel own FPGA firms, yet neither has implemented an FPGA-section in their silicon (AFAIK).
Especially, with Intel looking at 'trimming the fat' off X86, a small FPGA in-silicon (seems like it) could be handy for running legacy code in real hardware.
(Or 'offering for sale/subscription' tiered hardware acceleration. knowing Intel...)

Meteor Lake and Arrow Lake will sit on an FPGA interposer IIRC. And I think this is part of why Metero Lake is late. FPGA, tiles, new node(s) are proving difficult to get right

 

[persondb]

I just saw this tiny thing for 25$

$25 Sipeed Tang Nano 20K FPGA board can simulate a RISC-V core, run Linux, retro games - CNX Software

The Sipeed Tang Nano 20K is a low-cost FPGA development board based on Gowin GW2AR-18 FPGA with 20,736 logic cells and 64Mbit RAM, which coupled with

www.cnx-software.com

Not a lot of gates but plenty enough to get your feet wet

Well, how is software support for those? FPGAs die by bad toolchains. The other Tang Nanos boards are better though as at that price, you aren't competing with the Aliexpress Cyclones or Spartans, or hell, even a Zynq at $50 or so.