Intel Core Ultra 2-series "Arrow Lake-S" Desktop Features 4 Xe-core iGPU, No Island Cores

[btarunr]

Over the weekend, there have been a series of leaks from sources such as Golden Pig Upgrade, and High Yield YT, surrounding Intel's next-generation desktop processor, the Core Ultra 2-series "Arrow Lake-S." The lineup is likely to continue the new client processor naming scheme Intel introduced with the Core Ultra 1-series "Meteor Lake" on the mobile platform. "Arrow Lake-S" is rumored to debut the new Socket LGA1851, which retains cooler-compatibility with LGA1700. Although Intel has nucleated all I/O functions of the traditional PCH to "Meteor Lake," making it a single-chip solution on the mobile platform; and although the mobile "Arrow Lake" will continue to be single-chip; the desktop "Arrow Lake-S" will be a 2-chip solution. This is mainly because the desktop platform demands a lot more PCIe lanes, for a larger number of NVMe storage devices, or high bandwidth devices such as Thunderbolt and USB4 hubs, etc.

Another key finding in this latest series of leaks, is that unlike "Meteor Lake," the desktop "Arrow Lake-S" will do away with low-power island E-cores located in the SoC tile of the processor. All CPU cores are located in the Compute tile, which is expected to be built in the Intel 20A foundry node—the company's first node to implement GAAFETs (nanosheets), with backside power delivery; as well as an advanced 2nd generation EUV lithography. Intel's 1st Gen EUV is used on the current FinFET-based Intel 4 and Intel 3 foundry nodes.



The Compute tile is rumored to have an 8P+8E CPU core configuration. Each of the 8 "Lion Cove" P-cores features 3 MB of dedicated L2 cache, and the P-core architecture is said to offer an IPC uplift over the current "Redwood Cove" P-cores powering "Meteor Lake." Perhaps the biggest ISA change is the lack of Hyper-Threading for the P-cores. The E-core microarchitecture is "Skymont," with another round of IPC increases. At generational IPC growth-rate of Intel's E-cores, "Skymont" is expected to offer IPC comparable to the "Willow Cove" cores powering 11th Gen "Tiger Lake" mobile processors.

Intel tends to give its client desktop processors significantly smaller iGPUs than its mobile chips, and the trend continues with "Arrow Lake-S." Apparently the chip comes with the smallest version of the Xe-LPG+ iGPU, with just 4 Xe cores (64 EU, or 512 unified shaders). Intel will avoid the Arc Graphics branding for this iGPU, it will be called simply "Intel Graphics" followed by a 3-digit model number. Some of the lower processor SKUs could even have fewer Xe cores. This is consistent with what Intel is doing with "Meteor Lake," where only the iGPU models with 7 or 8 Xe cores get Arc Graphics branding, while the ones with fewer Xe cores, such as the Core Ultra 5 125U with 4 Xe cores, is branded "Intel Graphics."

Intel will include its 2nd Gen NPU (neural processing unit) with "Arrow Lake-S," making these the company's first desktop processors to support Intel AI Boost feature-set, which the company debuted with "Meteor Lake" on the mobile platform. Its first generation NPU offers a 10 TOPS AI inferencing performance at a significantly lower power footprint that having the AI workload executed on the CPU cores; and it's expected that Intel will nearly triple the performance of this NPU with "Arrow Lake."

Intel is expected to debut the Core Ultra 2-series "Arrow Lake-S" desktop processors in the second half of 2024.

View at TechPowerUp Main Site | Source

 

[Eternit]

I doubt early 20A process will have frequencies on pair with Raptor Lake refresh. Se even with higher IPC it might be only a bit faster in single thread. 8+8 without HT might be slower i multi thread.

 

[N/A]

6+8, according to the source. 14 core 14 threads this

 

[Daven]

The source says all tiles are TSMC on the mobile side. Only the desktop version gets 20A CPU tiles. This might explain the conflicting leaks on the process used for which tile.

 

[Wirko]

So if it turns out to be true and Intel is actually starting to abandon HT in P+E processors... It would mean that E cores are better than hyper-threads in several respects, which is my opinion too. I'm wondering what AMD's response will be, they should change something too in the long term, either substantially improve HT performance (which may be impossible in x86 designs) or kill it too.

 

[Eternit]

So if it turns out to be true and Intel is actually starting to abandon HT in P+E processors... It would mean that E cores are better than hyper-threads in several respects, which is my opinion too. I'm wondering what AMD's response will be, they should change something too in the long term, either substantially improve HT performance (which may be impossible in x86 designs) or kill it too.

HT gives you 20-25% multi thread performance almost for free. E cores give more, but requires a lot of more additional transistors. While in single thread scenario there is no difference, there is one when you need a few threads and some of them are more critical then other. Without scheduling optimisation a critical thread may share core resources with less important thread. This is common in gaming. So if you have less critical thread than P cores and other threads need less performance than E cores can provide, then it is better to have P cores without HT. This is usual scenario in games. On the other hand in scenarios when you have a lot of equal threads, having HT is beneficial. I wonder why they don't have HT on E cores as that would improve their efficiency.

 

[Daven]

So if it turns out to be true and Intel is actually starting to abandon HT in P+E processors... It would mean that E cores are better than hyper-threads in several respects, which is my opinion too. I'm wondering what AMD's response will be, they should change something too in the long term, either substantially improve HT performance (which may be impossible in x86 designs) or kill it too.

AMD tried something similar with Bulldozer. It failed spectacularly. I’m sure AMD has a plaque on a wall somewhere that says ‘Never Again’. SMT and dense cores with the same IPC as regular cores is the much, much, much better way to go than crippled E-cores.

 

[Noyand]

Similar IPC to tiger lake doesn't sound disgusting, but I wonder at which frequency those e-cores will run.

 

[Darmok N Jalad]

AMD tried something similar with Bulldozer. It failed spectacularly. I’m sure AMD has a plaque on a wall somewhere that says ‘Never Again’. SMT and dense cores with the same IPC as regular cores is the much, much, much better way to go than crippled E-cores.

I often wonder if Bulldozer, in concept, was simply just too far ahead of itself. It took the might and resources of Intel and MS to make heterogeneous CPUs work in the Windows scheduler, and even then it took some time to deal with the right process going to the right place. AMD had little chance of success with such a design back then. Not to say it was a great design, as it was also a guess in the wrong direction.

 

[Readlight]

Are they making again LGA 775 Core 2 quad extreme procesors

 

[Wirko]

Are they making again LGA 775 Core 2 quad extreme procesors

That's an exact description - except they aren't 775, aren't 2, aren't quad, and aren't extreme.

 

[phints]

Intel is so behind the competition in performance per watt and their naming has gotten so confusing it's just cringe to even look at these links anymore.

 

[Eternit]

I often wonder if Bulldozer, in concept, was simply just too far ahead of itself. It took the might and resources of Intel and MS to make heterogeneous CPUs work in the Windows scheduler, and even then it took some time to deal with the right process going to the right place. AMD had little chance of success with such a design back then. Not to say it was a great design, as it was also a guess in the wrong direction.

The problem with Buldozer was, it was 1.5core pretending to be dual core. It was cheaper to produce but had performance issue. To use it's full potential you need two threads one with and one without floating point calculations. In case of E core they are slower than P but two threads don't need to be different in types of operations.

 

[Minus Infinity]

I doubt early 20A process will have frequencies on pair with Raptor Lake refresh. Se even with higher IPC it might be only a bit faster in single thread. 8+8 without HT might be slower i multi thread.

Basically all leaks are saying huge clock frequency regressions with Arrow Lake. 5Gz will be best case.