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JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced upcoming raw card designs currently in development in JEDEC's JC-45 Committee for DRAM Modules in collaboration with the JC-40 and JC-42 Committees. These raw card memory device standards are intended for use in client computing applications such as laptops and desktops and will be supported by related appendix specifications. The forthcoming raw cards will also complement two DDR5 Clock Driver standards published earlier this year: JESD323: DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification and JESD324: DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification.
Integrating a Clock Driver (CKD) into a DDR5 DIMM provides numerous advantages, particularly in memory stability and performance, and enhances signal integrity and reliability at high speeds. By regenerating the clock signal locally on the DIMM, a CKD ensures stable operation even at elevated clock speeds. With a DDR5 CKD, DIMM data rates can be increased from 6400 Mbps to 7200 Mbps in the initial version of the standard, and targeting up to 9200 Mbps in future versions.
Available configurations include 1Rank x8, 1Rank x8 with EC4 (4-bit error correction), 2Rank x8, 2Rank x8 with EC4, and 1Rank x16.
"In light of industry demand and the need to ensure DDR5 operates reliably at high clock speeds, JEDEC views the addition of a clock driver as a vital solution to these challenges and to our commitment to advancing memory performance," said Mian Quddus, JEDEC Board of Directors Chairman.
"DIMM suppliers who are JEDEC members can provide advance solutions today, while non-member DIMM suppliers will be able to download design files once they are published by JEDEC," said John Kelly, JEDEC President. He added, "Membership grants access to pre-publication proposals and provides early insights into active projects like DDR5 CKD. Interested companies are encouraged to contact JEDEC to discover the benefits of membership and join today."
View at TechPowerUp Main Site | Source
Integrating a Clock Driver (CKD) into a DDR5 DIMM provides numerous advantages, particularly in memory stability and performance, and enhances signal integrity and reliability at high speeds. By regenerating the clock signal locally on the DIMM, a CKD ensures stable operation even at elevated clock speeds. With a DDR5 CKD, DIMM data rates can be increased from 6400 Mbps to 7200 Mbps in the initial version of the standard, and targeting up to 9200 Mbps in future versions.
Available configurations include 1Rank x8, 1Rank x8 with EC4 (4-bit error correction), 2Rank x8, 2Rank x8 with EC4, and 1Rank x16.
"In light of industry demand and the need to ensure DDR5 operates reliably at high clock speeds, JEDEC views the addition of a clock driver as a vital solution to these challenges and to our commitment to advancing memory performance," said Mian Quddus, JEDEC Board of Directors Chairman.
"DIMM suppliers who are JEDEC members can provide advance solutions today, while non-member DIMM suppliers will be able to download design files once they are published by JEDEC," said John Kelly, JEDEC President. He added, "Membership grants access to pre-publication proposals and provides early insights into active projects like DDR5 CKD. Interested companies are encouraged to contact JEDEC to discover the benefits of membership and join today."
View at TechPowerUp Main Site | Source
