Kioxia Develops OCTRAM (Oxide-Semiconductor Channel Transistor DRAM) Technology

[TheLostSwede]

Kioxia Corporation, a world leader in memory solutions, today announced the development of OCTRAM (Oxide-Semiconductor Channel Transistor DRAM), a new type of 4F2 DRAM, comprised of an oxide-semiconductor transistor that has a high ON current, and an ultra-low OFF current, simultaneously. This technology is expected to realize a low power DRAM by bringing out the ultra-low leakage property of the InGaZnO transistor. This was first announced at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, CA on December 9, 2024. This achievement was jointly developed by Nanya Technology and Kioxia Corporation. This technology has the potential to lower power consumption in a wide range of applications, including AI and post-5G communication systems, and IoT products.

The OCTRAM utilizes a cylinder-shaped InGaZnO vertical transistor (Fig.1) as a cell transistor. This design enables the adaptation of a 4F2 DRAM, which offers significant advantages in memory density compared to the conventional silicon-based 6F2 DRAM.




The InGaZnO vertical transistor achieves a high ON current of over 15μA/cell (1.5 x 10-5 A/cell) and an ultra-low OFF current below 1aA/cell (1.0 x 10-18 A/cell) through device and process optimization (Fig.2). In the OCTRAM structure, the InGaZnO vertical transistor is integrated on top of a high aspect ratio capacitor (capacitor-first process). This arrangement allows for the decoupling of the interaction between the advanced capacitor process and the InGaZnO performance (Fig.3).

InGaZnO is a compound of In (indium), Ga (gallium), Zn (zinc), and O (oxygen)

• This announcement has been prepared to provide information on our business and does not constitute or form part of an offer or invitation to sell or a solicitation of an offer to buy or subscribe for or otherwise acquire any securities in any jurisdiction or an inducement to engage in investment activity nor shall it form the basis of or be relied on in connection with any contract thereof.
• Information in this document, including product prices and specifications, content of services and contact information, is correct on the date of the announcement but is subject to change without prior notice.

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[Wirko]

InGaZnO is IGZO, a well known semiconducting material for thin film transistors. IGZO was discovered in 2003/2004 and presumably patented shortly after that. The patent has expired or is about to expire soon. Is this why we're hearing of this type of cell now?

(I understand it's not that simple, there seem to be a few patents related to IGZO and IGZO TFTs, one will only expire in 2030, etc. But there may still be something to what I said above.)

 

[TheLostSwede]

InGaZnO is IGZO, a well known semiconducting material for thin film transistors. IGZO was discovered in 2003/2004 and presumably patented shortly after that. The patent has expired or is about to expire soon. Is this why we're hearing of this type of cell now?

(I understand it's not that simple, there seem to be a few patents related to IGZO and IGZO TFTs, one will only expire in 2030, etc. But there may still be something to what I said above.)

No idea, but it's very possible.

 

[NoLoihi]

German Wikipedia (for some reason not the English one) has 1.6×10¯¹⁹A as one electron per second (I guess that’s plain physics) and, interestingly, a figure of 3fA (3×10¯¹⁵A) taken off a 2007’s book, for the leakage current of a typical DRAM cell. Now, I’m wondering, what are they going to do with that headroom? Make cells proportionally smaller? (How’s consistency among cells in the same chip? Can’t have some lose their charge much faster than others, when they’ll all be refreshed in the same interval.) https://de.wikipedia.org/wiki/Liste_von_Größenordnungen_der_elektrischen_Stromstärke https://books.google.de/books?id=PBR9RXxRnHUC

Does anyone know off the top of his mind if refreshes are not just a battery, but also a performance issue? There’s an Intel paper I’ve spotted right away, which claims a rather insane 17% impact versus hypothetical no refreshes on a DDR3 system with eight cores. https://users.ece.cmu.edu/~yoonguk/papers/chang-hpca14.pdf
So, I figure, maybe they’d want to cut down on refreshes instead. (Which, in turn, requires inter-cell consistency, as longer cycles would exacerbate any differences in charge loss between cells.)
Also Wikipedia claims (added at the very end of 2012) that cells were being refreshed every 64ms (swathes of time in hardware terms), with easy increases possible to 500ms if the chips are at room temperature instead of the top of their operating range, and further towards even the ten second mark (!) if you cut out the 1% of RAM with the weakest cells. This honestly seems like a no-brainer for energy savings, especially in standby, I wonder how many manufacturers have done this. (Conversely, in all untweaked computers, this would amount to a nice increase in stanby time. But yeah, maybe things have already moved on from 2012?) https://en.wikipedia.org/wiki/Memory_refresh#Refresh_interval

 

[Wirko]

German Wikipedia (for some reason not the English one) has 1.6×10¯¹⁹A as one electron per second (I guess that’s plain physics) and, interestingly, a figure of 3fA (3×10¯¹⁵A) taken off a 2007’s book, for the leakage current of a typical DRAM cell. Now, I’m wondering, what are they going to do with that headroom? Make cells proportionally smaller? (How’s consistency among cells in the same chip? Can’t have some lose their charge much faster than others, when they’ll all be refreshed in the same interval.) https://de.wikipedia.org/wiki/Liste_von_Größenordnungen_der_elektrischen_Stromstärke https://books.google.de/books?id=PBR9RXxRnHUC

Does anyone know off the top of his mind if refreshes are not just a battery, but also a performance issue? There’s an Intel paper I’ve spotted right away, which claims a rather insane 17% impact versus hypothetical no refreshes on a DDR3 system with eight cores. https://users.ece.cmu.edu/~yoonguk/papers/chang-hpca14.pdf
So, I figure, maybe they’d want to cut down on refreshes instead. (Which, in turn, requires inter-cell consistency, as longer cycles would exacerbate any differences in charge loss between cells.)
Also Wikipedia claims (added at the very end of 2012) that cells were being refreshed every 64ms (swathes of time in hardware terms), with easy increases possible to 500ms if the chips are at room temperature instead of the top of their operating range, and further towards even the ten second mark (!) if you cut out the 1% of RAM with the weakest cells. This honestly seems like a no-brainer for energy savings, especially in standby, I wonder how many manufacturers have done this. (Conversely, in all untweaked computers, this would amount to a nice increase in stanby time. But yeah, maybe things have already moved on from 2012?) https://en.wikipedia.org/wiki/Memory_refresh#Refresh_interval

You also need cell capacitance to do any meaningful calculations. This article from 2014 mentions 3.9 fF for an experimental cell, which is one-fifth that of (presumably) normal DRAM. Surprise surprise, the material used was InGaZnO.

The basic relation you need to know here is Q = C U
Q = charge in ampere-seconds, which corresponds to the number of electrons; an electron has a charge of 1.6×10¯¹⁹As
C = capacitance in farads, which depends on the dielectric (insulator) material, size and geometry of the cell
U = voltage in volts, which is what you actually read from a cell; probably around 1 V after writing, then diminishing because of leakage

Oh the joy of small units, fA, aF and the like. I'll probably mess up everything now.

So, for the numbers I and you quoted, roughly:
Q = 3.9 fF × 1 V = 3.9 fAs = 24,000 electrons stored in a "full" cell
and
3 fA = 19,000 electrons per second
which means that a cell could lose enough electrons in one second to become unreadable. (Ignoring exponential voltage and current drop here.)

I won't get started about MLC DRAM now. Maybe next time.