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AMD Expands 4th Gen EPYC CPU Portfolio with Processors for Cloud Native and Technical Computing Workloads

GFreeman

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Today, at the "Data Center and AI Technology Premiere," AMD announced the addition of two new, workload optimized processors to the 4th Gen EPYC CPU portfolio. By leveraging the new "Zen 4c" core architecture, the AMD EPYC 97X4 cloud native-optimized data center CPUs further extend the EPYC 9004 Series of processors to deliver the thread density and scale needed for leadership cloud native computing. Additionally, AMD announced the 4th Gen AMD EPYC processors with AMD 3D V-Cache technology, ideally suited for the most demanding technical computing workloads.

"In an era of workload optimized compute, our new CPUs is pushing the boundaries of what is possible in the data center, delivering new levels of performance, efficiency, and scalability," said Forrest Norrod, executive vice president and general manager, Data Center Solutions Business Group, AMD. "We closely align our product roadmap to our customers' unique environments and each offering in the 4th Gen AMD EPYC family of processors is tailored to deliver compelling and leadership performance in general purpose, cloud native or technical computing workloads."



Advancing Cloud Native Computing
Cloud native workloads are a fast-growing class of applications designed with cloud architecture in mind and are developed, deployed and updated rapidly. The AMD EPYC 97X4 processors, with up to 128 cores, deliver up to 3.7x throughput performance for key cloud native workloads compared to Ampere. Additionally, 4th Gen AMD EPYC processors, with "Zen 4c" cores, provide customers up to 2.7x better energy efficiency and support up to 3x more containers per server to drive cloud native applications at the greatest scale.

At the "Data Center and AI Technology Premiere," AMD was joined by Meta who discussed how these processors are well suited for their mainstay applications such as Instagram, WhatsApp and more; how Meta is seeing impressive performance gains with 4th Gen AMD EPYC 97X4 processors compared to 3rd Gen AMD EPYC across various workloads, while offering substantial TCO improvements over as well, and how AMD and Meta optimized the EPYC CPUs for Meta's power-efficiency and compute-density requirements.



Exceptional Technical Computing Performance
Technical computing enables faster design iterations and more robust simulations to help businesses design new and compelling products. 4th Gen AMD EPYC processors with AMD 3D V-Cache technology further extend the AMD EPYC 9004 Series of processors to deliver the world's best x86 CPU for technical computing workloads such as computational fluid dynamics (CFD), finite element analysis (FEA), electronic design automation (EDA) and structural analysis. With up to 96 "Zen 4" cores and an industry leading 1GB+ of L3 cache, 4th Gen AMD EPYC processors with AMD 3D V-Cache can significantly speed up product development by delivering up to double the design jobs per day in Ansys CFX.

On stage at the "Data Center and AI Technology Premiere," Microsoft announced the general availability of Azure HBv4 and HX instances, powered by 4th Gen AMD EPYC processors with AMD 3D V-Cache. Optimized for the most demanding HPC applications, the newest instances deliver performance gains of up to 5x when compared to the previous generation HBv3 and scale to hundreds of thousands of CPU cores.



The entire lineup of 4th Gen AMD EPYC processors is available today and are feature and socket compatible with existing AMD EPYC 9004 Series CPU-based systems, offering a seamless upgrade path.

View at TechPowerUp Main Site | Source
 
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That 16 core with 768MB L3 cache :eek:
 
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I am curious to see how Bergamo CPU compares in workloads with the best ARM or RISC architectures could offer. It's going to be super interesting.
 
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Lots of respect for AMD's engineers, they have an epyc instinct for modular design.

But one thing they can't do - well, not yet - is to put the existing 3D V-cache chip on top of the Zen 4c die. The arrangement of L3 cache sections on that die almost certainly makes it impossible.
 
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What's the purpose of a single thread variant when it uses same power and clocks as the SMT version. Is it half the price?
 
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What's the purpose of a single thread variant when it uses same power and clocks as the SMT version. Is it half the price?
Probably is price cut, otherwise there would be no reason to offer it, probably isn't half but cut price for 20% perf cut and for cheaper licensing of per/core software.
 
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Can I get some CPU cores with my cache, please? :ohwell:
 
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What's the purpose of a single thread variant when it uses same power and clocks as the SMT version. Is it half the price?
Some enterprise software is licensed per thread, so on SMT processors you are paying double for less than double performance. It makes sense in those instances to have a non-SMT variant to save through life costs.
 
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Many reasons, but I think the biggest one is that cache would have to be stacked on top of cores. That's a big no no because it's impossible to cool, cores creating a lot of heat and cache on top of it would insulate it. Curent Zen4 + 3D Cache works because 3D cache is stacked on top of cache.
 
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Yes but couldn't they theoretically stack less cache (smaller dies) & make it work?
 
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Some enterprise software is licensed per thread, so on SMT processors you are paying double for less than double performance. It makes sense in those instances to have a non-SMT variant to save through life costs.
Ah yes I forgot about that.
 
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Yes but couldn't they theoretically stack less cache (smaller dies) & make it work?
They could. What I meant was that they can't use the same cache die design for both Zen 4 and 4c.
 
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What's the purpose of a single thread variant when it uses same power and clocks as the SMT version. Is it half the price?
Likely one of two scenarios:

  1. Enough logic dies have damaged areas that are where the SMT technology is handled to warrant selling non-SMT CPU parts.
  2. There are likely software related scenarios where the weaker SMT threads could possibly hinder performance in some scenarios.
 
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