AMD "Matisse" and "Rome" IO Controller Dies Mapped Out

[btarunr]

Here are the first detailed die maps of the I/O controller dies of AMD's "Matisse" and "Rome" multi-chip modules that make up the company's 3rd generation Ryzen and 2nd generation EPYC processor families, respectively, by PC enthusiast and VLSI engineer "Nemez" aka @GPUsAreMagic on Twitter, with underlying die-shots by Fitzchens Fitz. The die maps of the "Matisse" cIOD in particular give us fascinating insights to how AMD designed the die to serve both as a cIOD and as an external FCH (AMD X570 and TRX40 chipsets). At the heart of both these chips' design effort is using highly configurable SerDes (serializer/deserializers) that can work as PCIe, SATA, USB 3, or other high-bandwidth serial interfaces, using a network of fabric switches and PHYs. This is how motherboard designers are able to configure the chipsets for the I/O they want for their specific board designs.

The "Matisse" cIOD has two x16 SerDes controllers and an I/O root hub, along with two configurable x16 SerDes PHYs, while the "Rome" sIOD has four times as many SerDes controllers, along with eight times as many PHYs. The "Castle Peak" cIOD (3rd gen Ryzen Threadripper) disables half the SerDes resources on the "Rome" sIOD, along with half as many memory controllers and PHYs, limiting it to 4-channel DDR4. The "Matisse" cIOD features two IFOP (Infinity Fabric over Package) links, wiring out to the two "Zen 2" CCDs (chiplets) on the MCM, while the "Rome" sIOD features eight such IFOP interfaces for up to eight CCDs, along with IFIS (Infinity Fabric Inter-Socket) links for 2P motherboards. Infinity Fabric internally connects all components on both IOD dies. Both dies are built on the 12 nm FinFET (12LP) silicon fabrication node at GlobalFoundries.



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[jeremyshaw]

Very cool! Interesting that AMD kept the 32 main SerDes connections (nominally 32 PCIe lanes) on the Matisse I/O die. It was there with Zeppelin, and they were used in that layout (for 64-128 PCIe lanes in Threadripper and Epyc, which had [originally] 2-4 Zeppelin dies).

I suppose future Epyc D/Embedded products will need the 32 SerDes lanes for PCIe/10GbE lines, so may as well bake it in now.

 

[mtcn77]

Any fans of Caesar 3? This reminds me of the city blocks constricted into a tight loop. Very hard to do unless you know a trick called 'forced walker'. I can see where the effort went, it is actually tougher to remake using the same framework. Have to have a shift in mindset.
It is remarkable what has transpired over the last decade. I can recall when Intel designers, as talented as they are, providing honest commentary to the inner workings of a good design had their david vs goliath moment when AMD put up a challenge with automated semicustom designs to their hand picked design. You couldn't make this up even if you tried. PR homecoming.

 

[Valantar]

Am I the only one wondering what "c" in "cIOD" stands for? CCD = Core Complex Die, cIOD = ??? Input Output Die?

 

[Nioktefe]

Am I the only one wondering what "c" in "cIOD" stands for? CCD = Core Complex Die, cIOD = ??? Input Output Die?

"AMD "Matisse" cIOD and "Rome" sIOD. " From the source's twitter

So my guess would be consumer IOD and server IOD

 

[Valantar]

"AMD "Matisse" cIOD and "Rome" sIOD. " From the source's twitter

So my guess would be consumer IOD and server IOD

That does kind of make sense, though it's a weird distinction to apply given that there are consumer versions of the Rome IOD with just some parts disabled (Threadripper 3000), and enterprise/workstation versions of the Matisse IOD (both as the TRX40 chipset as well as in Ryzen Pro CPUs). Seems like a distinction without a difference to me. Calling one the "Matisse IOD" and the other the "Rome IOD" ought to be plenty clear as to the difference in silicon, no?

 

[Nemez]

That does kind of make sense, though it's a weird distinction to apply given that there are consumer versions of the Rome IOD with just some parts disabled (Threadripper 3000), and enterprise/workstation versions of the Matisse IOD (both as the TRX40 chipset as well as in Ryzen Pro CPUs). Seems like a distinction without a difference to me. Calling one the "Matisse IOD" and the other the "Rome IOD" ought to be plenty clear as to the difference in silicon, no?

sIOD/cIOD makes a decent amount of sense, calling it "Matisse IOD" and "Rome IOD" has the same issue, since Threadripper is technically not "Rome", but rather "Castle Peak"

Very cool! Interesting that AMD kept the 32 main SerDes connections (nominally 32 PCIe lanes) on the Matisse I/O die. It was there with Zeppelin, and they were used in that layout (for 64-128 PCIe lanes in Threadripper and Epyc, which had [originally] 2-4 Zeppelin dies).

I suppose future Epyc D/Embedded products will need the 32 SerDes lanes for PCIe/10GbE lines, so may as well bake it in now.

Why they kept 32 lanes? They had to, keep in mind this same die is also used as the X570 and TRX40 chipsets, both of which utilize the full 12 USB controllers, 4 SATA lanes, 2 vendor configurable x4 links, a general purpose x8 link and either a x4 or x8 CPU uplink, that adds up to a total of 24 SerDes required for X570 and 28 SerDes for TRX40

 

[Valantar]

sIOD/cIOD makes a decent amount of sense, calling it "Matisse IOD" and "Rome IOD" has the same issue, since Threadripper is technically not "Rome", but rather "Castle Peak"

Still a distinction without a difference. "Castle Peak IOD" is not the same as "Rome IOD" after all - it's based on the same silicon, but has half of it disabled. Attaching a letter to denominate a market segment that is already denominated by the platform code name is just unnecessary and confusing. Naming it after its implementation sounds like the only way to have a consistent and clear naming scheme. It also avoids attaching unrelated letters to an abbreviation - I/O is I/O no matter if it's in a server or consumer application after all.