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Semiconductor intellectual property core provider CAST today announced a new IP core that implements the SNOW-V stream cipher algorithm to meet the security and performance demands of modern communication systems. Available now for ASICs or FPGAs, the company believes it to be the first such commercial IP core.
The new SNOW-V Stream Cipher Engine provides a flexible and reusable hardware implementation of the official SNOW-V mechanism as published in 2019 by the IACR Transactions on Symmetric Cryptology. SNOW-V revises the SNOW 3G stream cipher algorithm to help satisfy the high-speed, low-latency security requirements of 5G, 6G, and future mobile networks. The core:
"Security safeguards struggle to keep up with the dramatic increases in the speed and bandwidth of cellular communications, multimedia streaming capabilities, and Internet of Things communication complexity," said Dr. George Athanasiou, security product manager for CAST. "This new SNOW-V core joining CAST's proven, low-risk IP cores line means system designers can now establish high-speed security with practically no effort or performance impact."
Editor's note: The following information has been added from CAST SNOW-V Stream Cipher Engine documentation
ASIC Implementation results
The SNOW-V core can be mapped to any ASIC technology. The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
Altera Implementation results
The SNOW-V core can be mapped to any Altera FPGA device. The following are sample Altera FPGA pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
AMD Implementation results
The SNOW-V core can be mapped to any AMD FPGA device. The following are sample AMD FPGA pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
View at TechPowerUp Main Site | Source
The new SNOW-V Stream Cipher Engine provides a flexible and reusable hardware implementation of the official SNOW-V mechanism as published in 2019 by the IACR Transactions on Symmetric Cryptology. SNOW-V revises the SNOW 3G stream cipher algorithm to help satisfy the high-speed, low-latency security requirements of 5G, 6G, and future mobile networks. The core:
- Is optimized for ultra-high-speed communication, delivering throughput rates of over 140 Gbps in ASIC and 65 Gbps in FPGA implementations
- Ensures confidentiality and integrity with AEAD (Authenticated Encryption with Associated Data) capabilities by easily interoperating with a GMAC (Galois Message Authentication Code) security framework in a GCM (Galois/Counter mode) topology
- Seamlessly upgrades existing 4G/5G network encryption as a drop-in replacement for SNOW 3G.
"Security safeguards struggle to keep up with the dramatic increases in the speed and bandwidth of cellular communications, multimedia streaming capabilities, and Internet of Things communication complexity," said Dr. George Athanasiou, security product manager for CAST. "This new SNOW-V core joining CAST's proven, low-risk IP cores line means system designers can now establish high-speed security with practically no effort or performance impact."
Editor's note: The following information has been added from CAST SNOW-V Stream Cipher Engine documentation
ASIC Implementation results
The SNOW-V core can be mapped to any ASIC technology. The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
Altera Implementation results
The SNOW-V core can be mapped to any Altera FPGA device. The following are sample Altera FPGA pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
AMD Implementation results
The SNOW-V core can be mapped to any AMD FPGA device. The following are sample AMD FPGA pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
View at TechPowerUp Main Site | Source