- Joined
- Aug 19, 2017
- Messages
- 2,582 (0.97/day)
Chiplet design of processors is getting more popular due to many improvements and opportunities it offers. Some of the benefits include lower costs as the dies are smaller compared to one monolithic design, while you are theoretically able to stitch as much of the chiplets together as possible. During the ISSCC 2020 conference, CEA-Leti, a French research institute, created a 96 core CPU made from six 3D stacked 16 core chiplets. The chip is created as a demonstration of what this modular approach offers and what are the capabilities of the chiplet-based CPU design.
The chiplets are manufactured on the 28 nm FD-SOI manufacturing process from STMicroelectronics, while the active interposer die below them that is connecting everything is made using the 65 nm process. Each one of the six dies is housing 16 cores based on MIPS Instruction Set Architecture core. Each chiplet is split into four 4-core clusters that make up for a total of 16 cores per chiplet. When it comes to the core itself, it is a scalar MIPS32v1 core equipped with 16 KiB of L1 instruction and an L1 data cache. For L2 cache, there is 256 KiB per cluster, while the L3 cache is split into four 1 MiB tiles for the whole cluster. The chiplets are stacked on top of an active interposer which connects the chiplets and provides external I/O support.
To connect the chiplets, each die has four unique connectors called the "3D Plug", which is a die-to-die interface. It achieves a throughput of 3 TB/s/mm², while its power efficiency is rated at 0.59 pico Joules per bit. The chip operates at 130 MHz frequency at 0.5 V power, however, it can run at 1.1 GHz given a 1.1 V of power.
View at TechPowerUp Main Site
The chiplets are manufactured on the 28 nm FD-SOI manufacturing process from STMicroelectronics, while the active interposer die below them that is connecting everything is made using the 65 nm process. Each one of the six dies is housing 16 cores based on MIPS Instruction Set Architecture core. Each chiplet is split into four 4-core clusters that make up for a total of 16 cores per chiplet. When it comes to the core itself, it is a scalar MIPS32v1 core equipped with 16 KiB of L1 instruction and an L1 data cache. For L2 cache, there is 256 KiB per cluster, while the L3 cache is split into four 1 MiB tiles for the whole cluster. The chiplets are stacked on top of an active interposer which connects the chiplets and provides external I/O support.
To connect the chiplets, each die has four unique connectors called the "3D Plug", which is a die-to-die interface. It achieves a throughput of 3 TB/s/mm², while its power efficiency is rated at 0.59 pico Joules per bit. The chip operates at 130 MHz frequency at 0.5 V power, however, it can run at 1.1 GHz given a 1.1 V of power.
View at TechPowerUp Main Site
