Intel "Meteor Lake" 2P+8E Silicon Annotated

[btarunr]

Le Comptoir du Hardware scored a die-shot of a 2P+8E core variant of the "Meteor Lake" compute tile, and Locuza annotated it. "Meteor Lake" will be Intel's first processor to implement the company's IDM 2.0 strategy to the fullest. The processor is a multi-chip module of various tiles (chiplets), each with a certain function, sitting on die made on a silicon fabrication node most suitable to that function. Under this strategy, for example, if Intel's chip-designers calculate that the iGPU will be the most power-hungry component on the processor, followed by the CPU cores, the graphics tile will be built on a more advanced process than the compute tile. Intel's "Meteor Lake" and "Arrow Lake" processors will implement chiplets built on the Intel 4, TSMC N3, and Intel 20A fabrication nodes, each with unique power and transistor-density characteristics. Learn more about the "Meteor Lake" MCM in our older article.

The 2P+8E (2 performance cores + 8 efficiency cores) compute tile is one among many variants of compute tiles Intel will develop for the various SKUs making up the next-generation Core mobile processor series. The die is annotated with the two large "Redwood Cove" P-cores and their cache slices taking up about 35% of the die area; and the two "Crestmount" E-core clusters (each with 4 E-cores), and their cache slices, taking up the rest. The two P-cores and two E-core clusters are interconnected by a Ring Bus, and share an L3 cache. The size of each L3 cache slice is either 2.5 MB or 3 MB. At 2.5 MB, the total L3 cache will be 10 MB, and at 3 MB, it will be 12 MB. As with all past generations, the L3 cache is fully accessible by all CPU cores in the compute tile.



Each "Redwood Cove" P-core has 2 MB of dedicated L2 cache, an upgrade from the 1.25 MB on "Golden Cove" P-cores. Intel will make several upgrades to the core to increase IPC over "Golden Cove." Each "Crestmont" E-core cluster sees four "Crestmont" E-cores share a 4 MB L2 cache—double that of the 2 MB in "Gracemont" E-core clusters in "Alder Lake" processors. These cores will feature higher IPC, and probably be able to sustain higher clock speeds; as well as benefit from the larger L2 cache.

The CPU cores and last-level cache are the only identifiable components on the compute die. The rest of it could feature a limited-function Uncore component with the interconnect that binds the various tiles together.

View at TechPowerUp Main Site | Source

 

[napata]

I doubt we see a regression in size of the L3 slices so most likely it's 3 MB.

 

[PapaTaipei]

I was tickling with this idea since a long time: Intel could bury NVIDIA by making a CPU+GPU on a single die. Killing the gaming GPU market. They won't do it because the shareholders of both companies are the same people.

 

[dj-electric]

I was tickling with this idea since a long time: Intel could bury NVIDIA by making a CPU+GPU on a single die. Killing the gaming GPU market. They won't do it because the shareholders of both companies are the same people.

That's a bit of a happy wish in a world where maximizing profits isn't boiled down to making a crazy expensive silicon that needs crazy expensive and high capacity memory, and puts out crazy amounts of heat.

Intel will make more powerful SoCs for gaming, but more in the style of what AMD does, especially in devices like the SteamDeck.

At the moment, they do not seem interested in making powerful SoCs for the desktop market with beefy GPUs.

 

[tabascosauz]

I was tickling with this idea since a long time: Intel could bury NVIDIA by making a CPU+GPU on a single die. Killing the gaming GPU market. They won't do it because the shareholders of both companies are the same people.

They won't do that on one "die" because it would be way too honking big of a monolithic die on their current cutting edge process to make any kind of financial sense for any company.

But if you mean in one "package", they already paved the way for that 5 years ago, in Kaby-G:

Hot Chips 30: Intel Kaby Lake G

A look at Intel's current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

fuse.wikichip.org

If you were referring to CPU+GPU as a single processor, then you've just described an APU. Rembrandt is fast, but APUs will forever be playing catchup unless something radical changes, and Intel isn't immune from those challenges.

 

[nicamarvin]

This is a Mock Up of a 8 + 8 Meteor Lake CPU Tile compared to a 8 + 8 Alder lake compute section, they look identical

Meteor Lake 8 + 8

Alder Lake 8 + 8

Edit.

@btarunr Golden Cove is capable of 2 MiB of L2 on Sapphire Rapids, the client side received a reduced amount, but it's coming back to full 2 MiB on Raptor Lake.

 

[AnarchoPrimitiv]

It irks me to see TSMC N3 on there....if Intel throwing around a bunch of money results in AMD delaying Zen5 because they can't get access to 3nm, we'll all be regretting that day

 

[ModEl4]

I doubt we see a regression in size of the L3 slices so most likely it's 3 MB.

Exactly!
A logical thought that Locuza could have made himself, maybe he was in disbelief regarding the density that Intel achieved for the L3?

 

[nicamarvin]

Exactly!
A logical thought that Locuza could have made himself, maybe he was in disbelief regarding the density that Intel achieved for the L3?

Golden Cove, Raptor Cove and Redwood Cove all have 3 MiB per core. There are not exceptional/additional density gains to be found here.

 

[ModEl4]

Golden Cove, Raptor Cove and Redwood Cove all have 3 MiB per core. There are not exceptional/additional density gains to be found here.

I didn't imply exceptional density gains.
From 28nm and forward the density scaling for cache is especially challenging in relation with the pre finfet era. Locuza hypothesize that it was either 2.5MB or 3MB. So i guess his impression based on the die analysis was somewhere in the middle and couldn't decide between the two.
Middle is 2.75MB, so less than -9% vs the 3MB figure, so i was not implying anything exceptional, just enough to leave him undecided, just a guess.

 

[nicamarvin]

Meteor Lake 6+8 and 8+8 Die pictures(twitter source deleted)

2P + 8E Compute Tile

6P + 8E

8P + 16E