PCI-SIG Announces PCI Express 7.0 Specification to Reach 128 GT/s

[btarunr]

PCI-SIG today announced that the PCI Express (PCIe ) 7.0 specification will double the data rate to 128 GT/s and is targeted for release to members in 2025. "For 30 years the guiding principle of PCI-SIG has been, 'If we build it, they will come,'" observed Nathan Brookwood, Research Fellow at Insight 64. "Early parallel versions of PCI technology accommodated speeds of hundreds of megabytes/second, well matched to the graphics, storage and networking demands of the 1990s.

In 2003, PCI-SIG evolved to a serial design that supported speeds of gigabytes/second to accommodate faster solid-state disks and 100MbE Ethernet. Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. Today's announcement of PCI-SIG's plan to double the channel's speed to 512 GB/s (bi-directionally) puts it on track to double PCIe specification performance for another 3-year cycle."



PCI-SIG technical workgroups will be developing the PCIe 7.0 specification with the following feature goals:

• Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
• Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
• Focusing on the channel parameters and reach
• Continuing to deliver the low-latency and high-reliability targets
• Improving power efficiency
• Maintaining backwards compatibility with all previous generations of PCIe technology

"With the forthcoming PCIe 7.0 specification, PCI-SIG continues our 30-year commitment to delivering industry-leading specifications that push the boundaries of innovation," said Al Yanes, PCI-SIG President and Chairperson. "As PCIe technology continues to evolve to meet the high bandwidth demands, our workgroups' focus will be on channel parameters and reach and improving power efficiency."

The PCIe 7.0 specification is targeted to support emerging applications such as 800 G Ethernet, AI/ML, Cloud and Quantum Computing; and data-intensive markets like Hyperscale Data Centers, High-Performance Computing (HPC) and Military/Aerospace.

View at TechPowerUp Main Site

 

[catulitechup]

Well Well amd will be happy because them stay ready for future x400/x500 xt card with 0.5 lanes XXDDD because 1 lane is too much for users (lisa su asking for who think in our shareholders and in next lisa su bugatti)

 

[P4-630]

We're in a hurry now huh!

 

[bonehead123]

Well, I'll be damned....

They are FINALLY catching up to my pcie-218.74 rig with 681.59ZB of ram, which I've had running since 2002, bout friggin time.....hahahahaha

And in case you were wondering, those triangle shaped guys that built the pyramids leased it to me, for about 536 years, or until they come back this way again....

 

[Minus Infinity]

And I thought I was joking when I said a few months ago I'm skipping PCI-E 6 for 7. Why announce something many years from coming out, who cares. This will be like 2026+ for sure.

 

[Arkz]

Let's skip 5 and 6 and just go straight to this!

 

[mechtech]

Is that enough for minecraft??

 

[IceShroom]

The bandwidth numbers seems to be off by 2x.

 

[DeathtoGnomes]

The real test would be if its USB-C compatible.

 

[ARF]

And I thought I was joking when I said a few months ago I'm skipping PCI-E 6 for 7. Why announce something many years from coming out, who cares. This will be like 2026+ for sure.

Imagine a 2027 PC.
Graphics card: AMD Radeon 11550 XT PCIe 7.0 x1.
Monitor: model year 1989 1920x1080.
Internet speed: 10 MBit.
Windows 10.

 

[stimpy88]

Anyone can simply draw up a white paper spec and claim double bandwidth blah blah, but it's the engineers implementing this that are starting to have the nightmares. PCie 4 was tricky, and even Intel are struggling with PCie 5. We are hearing that motherboard designers are struggling with signal integrity. I can't imagine that PCie 6 won't need some drastic and probably expensive changes to make it happen at consumer level. PCie 7 is unobtainium unless they have mitigated the signalling issues, which they do not mention here.

One thing I do see coming, is reducing the amount of lanes a graphics card will have access to, I would not be surprised to hear of the standard shifting to a x8 interface instead when we get to PCie6, to help get round these signal issues.

 

[bogami]

That they are lagging behind the announced performances of higher bandwidth, but is it really that difficult to reach consents or permits to raise operating frequencies and produce support electronics? The old and the new are gaining an ever-increasing gap, and regardless of the FPS, the differences are not worth mentioning.

 

[BlaezaLite]

I'm still on Pcie 3! Fuck off and calm down with the progression! Might end up back on an Xbox at this rate...

 

[ARF]

Anyone can simply draw up a white paper spec and claim double bandwidth blah blah, but it's the engineers implementing this that are starting to have the nightmares. PCie 4 was tricky, and even Intel are struggling with PCie 5. We are hearing that motherboard designers are struggling with signal integrity. I can't imagine that PCie 6 won't need some drastic and probably expensive changes to make it happen at consumer level. PCie 7 is unobtainium unless they have mitigated the signalling issues, which they do not mention here.

One thing I do see coming, is reducing the amount of lanes a graphics card will have access to, I would not be surprised to hear of the standard shifting to a x8 interface instead when we get to PCie6, to help get round these signal issues.

The thing is that it is worthless, stupid and expensive.
Simply stay with PCIe 4.0 x16 until it becomes a major bottleneck, like the current state of mechanical HDD is.

 

[DeathtoGnomes]

Simply stay with PCIe 4.0 x16 until it becomes a major bottleneck, like the current state of mechanical HDD is.

Dont pick on the HDD... Antiques are only valuable for so long as they still work.

 

[aQi]

PCI-SIG is on fire.

 

[The Von Matrices]

In 2003, PCI-SIG evolved to a serial design that supported speeds of gigabytes/second to accommodate faster solid-state disks and 100MbE Ethernet.

Nice rewriting of history PCI-SIG. No one in the late '90s/early 2000s was thinking of ubiquitous SSDs when designing the first generation of PCIe. The bandwidth concerns at that time were for graphics cards, gigabit ethernet, and SCSI/SATA controllers.