Suggestion for TS: Separate P-Cores and E-Cores, just like Cache is separated in FIVR

[StarRacer]

I recently bought an MSI laptop with an Intel Core i9-14900HX. Out of habit, I undervolted it using ThrottleStop and managed to achieve a maximum of -100 mV on the CPU Core. Looks like I didn't win the silicon lottery (at least not in p cores) Beyond that, I started getting blue screens during stress tests in OCCT.

Later, I read forums and posts on Reddit and discovered that it’s possible to undervolt P-Cores and E-Cores separately in intel extreme tuning utility (Simply select all p cores and specify the offset, the same for e cores, using shift select the cores and specify the offset).

To my surprise, I was able to undervolt the E-Cores to -190 mV, which increased their frequencies while keeping the P-Cores at -100 mV.

To be safe, I set the E-Cores to -170 mV for stability. I tested this setup for a couple of days, and it worked perfectly even without any WHEA errors. This clearly shows that it makes sense to undervolt P-Cores and E-Cores separately. Since a stronger offset can be applied to E cores. Maximum -100 on P core and -190 on E core at my machine.

My Benchmarks (Tests with undervolting of only the core, no changes to the cache):

• Frequencies with global undervolting (all cores) in TS: P ~43.58 E ~34.45 (offset -100 in TS)
• TS Bench time with global undervolting (960M): 46,533
  
  
• Frequencies with separate undervolting for P and E cores in Intel ETU: P ~44,87 E ~39,41 (P offset -100, E offset -190)
• TS Bench time with separate undervolting (960M): 43,106
  
  !!! My tests are not accurate, so I would like others to check and confirm this !!!

Additional Observations:
I also noticed that P-Cores seem to operate in a sort of cluster. This means changing values for individual P-Cores is pointless since only one core applies the undervolting setting to all the others. If you try to apply undervolting to the other P-Cores individually (except the main one), nothing happens.
Therefore, if you plan to add this feature, just separate P-Cores and E-Cores. There’s no point in making it like Intel XTU, where each core can be adjusted individually.

What I came to:
Since I don't want to use Intel XTU and because i can't do it in TS, I use TS only for profiles to control turbo boost, I did undervolting in BIOS by switching the "VF Configuration Scope" setting to "Per-Core" mode, which allowed me to specify offsets for P cores and E cores separately. Because, I have configured everything via BIOS, so I have played it safe and indicated the values for everyday use below. P core -90 and E core -170

 

[unclewebb]

TS Bench time

I would not use the TS Bench results to determine anything. There are times when tasks will end up on P cores and you will get much better performance compared to running the same benchmark settings and having Windows or Intel assign more TS Bench threads to the E cores. Results of this benchmark can vary significantly even without any changes to one's settings.

it’s possible to undervolt P-Cores and E-Cores separately in intel extreme tuning utility

I have never had access to a modern Intel CPU with P and E cores while developing ThrottleStop. My 14900HX arrived just after releasing TS 9.7. This will allow me to finally do some hands on testing so I can hopefully improve ThrottleStop further.

I have always assumed that the setting in ThrottleStop that is labelled as E Cache actually controls both the E cache and E core voltage. This voltage is separate from the P core voltage control. I plan to do some XTU vs TS testing in the near future to see if this is true or not.

and managed to achieve a maximum of -100 mV on the CPU Core

Most 14900HX owners can go far beyond that when ThrottleStop is setup correctly. In TS 9.6, setting the mV Boost feature to 150 can improve stability when trying to use a large core / cache undervolt. Are you using the mV Boost setting?

In TS 9.7 you can enter the mV Boost value directly into the ThrottleStop V/F table for the core and the cache. Some extra voltage at low MHz helps with light load instability when using a big undervolt.

After undervolting with XTU, try running ThrottleStop but before running TS, delete the ThrottleStop.INI configuration file. This will allow ThrottleStop to read from the CPU the voltages that XTU is using. That might help answer the question whether E core and E cache voltage are the same thing. I originally called this voltage E cache because that is what HWiNFO was calling it.

Without access to the full Intel documentation and without any access to hardware, I have been depending on user feedback. Thank you for your suggestions and observations. Hopefully future versions of ThrottleStop will allow you to control everything that needs to be controlled some day soon.

 

[StarRacer]

I would not use the TS Bench results to determine anything. There are times when tasks will end up on P cores and you will get much better performance compared to running the same benchmark settings and having Windows or Intel assign more TS Bench threads to the E cores. Results of this benchmark can vary significantly even without any changes to one's settings.


I have never had access to a modern Intel CPU with P and E cores while developing ThrottleStop. My 14900HX arrived just after releasing TS 9.7. This will allow me to finally do some hands on testing so I can hopefully improve ThrottleStop further.

I have always assumed that the setting in ThrottleStop that is labelled as E Cache actually controls both the E cache and E core voltage. This voltage is separate from the P core voltage control. I plan to do some XTU vs TS testing in the near future to see if this is true or not.

View attachment 377841



Most 14900HX owners can go far beyond that when ThrottleStop is setup correctly. In TS 9.6, setting the mV Boost feature to 150 can improve stability when trying to use a large core / cache undervolt. Are you using the mV Boost setting?

In TS 9.7 you can enter the mV Boost value directly into the ThrottleStop V/F table for the core and the cache. Some extra voltage at low MHz helps with light load instability when using a big undervolt.

View attachment 377842

After undervolting with XTU, try running ThrottleStop but before running TS, delete the ThrottleStop.INI configuration file. This will allow ThrottleStop to read from the CPU the voltages that XTU is using. That might help answer the question whether E core and E cache voltage are the same thing. I originally called this voltage E cache because that is what HWiNFO was calling it.

Without access to the full Intel documentation and without any access to hardware, I have been depending on user feedback. Thank you for your suggestions and observations. Hopefully future versions of ThrottleStop will allow you to control everything that needs to be controlled some day soon.

I compared the values. It's funny that under load on the processor (TS Bench or stress test), the Offset "CPU Core" in TS value constantly changes -0.0996 then -0.1699 and again -0.0996 and so on until the load goes away.

When trying to give -190 to P cores, the laptop simply turns off, which means that Offset CPU Core in TS for some reason reads information in turn during load.


I also did a separate undervolting of P cores without E cores, the frequencies increased only on P cores, then I tried only E cores and the frequencies increased only on E cores and very much, perhaps because the offset is -190. I thought it would be distributed across all cores, but it looks like undervolting e cores only affects e cores and only their frequency is raised, while undervolting p cores allows for higher frequencies only on p cores. Perhaps because they are in different clusters.



Frequencies with undervolting only P cores during stress test:



P cores ~37,92 (-100)
E cores ~34,95 (-0)


Frequencies with undervolting E cores and P cores during stress test:


P cores ~37,91 (-100)
E cores ~40,15 (-190)


Cache during testing was 0 on p and e cores.

 

[unclewebb]

the Offset "CPU Core" in TS value constantly changes -0.0996 then -0.1699 and again -0.0996 and so on until the load goes away.

I wrote a small testing tool when Intel first introduced the FIVR in their 4th Gen CPUs. This tool allows me to read and write voltage information directly to the CPU FIVR without needing to run Intel XTU or ThrottleStop. That prevents either program from interfering with the results.

Intel CPUs have two types of registers. Some registers are core based so each individual core or thread of each core can be written to a different value. Most registers tend to be package based. If you write a value to any core or thread within a package based register, this same information will go to every core and every thread of this register within the CPU package. When you read information from a package based register, it does not matter what core the monitoring tool is running on. All cores and threads are set to the exact same value so all cores will return the same data.

For a test I decided to write an offset voltage value to a single P core. This value got written to all of the P cores and it also got written to all of the E cores. When I write 0 to the P core offset register to clear it, all of the offset voltage values in all of the CPU P cores and E cores are cleared at the same time. The exact same thing happens if I write an offset voltage value to only a single E core. This same value is written equally to all P cores and to all of the E cores. This is telling me that the CPU voltage control register is package based. At any moment in time, all of the P cores and all of the E cores are using the same offset voltage information in this single register.

Intel XTU showing that there is a P core voltage register that is completely separate from the E core voltage register does not seem to be true based on the testing I did today.

What is Intel XTU doing? My best guess is that Intel XTU is constantly varying the single core voltage register back and forth between two different voltage values. I do not know how many times per second XTU is doing this. The algorithm that Intel XTU is using to vary the voltage might be based on load or CPU temperature or which way the wind is blowing. The ThrottleStop FIVR monitoring table seems to confirm that this constant voltage switching is happening. If you completely exit Intel XTU, the voltage swapping algorithm should immediately stop.

I am looking forward to doing a lot more 14900HX testing in 2025.

Edit - Your ThrottleStop FIVR screenshot shows that you are using a very old microcode version, 11F. Consider updating to the latest BIOS version. Do some research about the stability issues with Intel 13th and 14th Gen processors. These issues have most likely been fixed but only if you update to the latest microcode version. Some laptop manufacturers are way too slow releasing BIOS updates. The latest microcode is version 12B. If you update the BIOS and it does not include the latest microcode version, you can easily install this patch so it is applied to the CPU each time Windows boots up.

@THEBOSS619 gets a gold star for posting this useful thread.

[INTEL]-How To Update Your Microcode for Intel HX 13/14th Gen. CPUs Laptops/Mobile Easily.

Let me start with a small background info... Since we know all Intel's fiasco about what is happening with Raptor Lake/Raptor Lake Refresh which is Intel's codename for the 13th and 14th generations of Intel Core processors, Most OEM/Vendors doesn't want to provide BIOS update that includes...

www.techpowerup.com

 

[StarRacer]

I made sure that Intel XTU was disabled and set the settings via BIOS and the behavior was almost exactly the same. But the constant change of the offset indicator in TS disappeared. Without load, it shows the offset that was set for P cores, and under load it shows the offset that was set for E cores, without jumps back and forth, it changes only under load.



I also did a test with OC disabled in BIOS.
And the results dropped to:
P cores ~35.44 (-0)
E cores ~33.86 (-0)

Some laptop manufacturers are way too slow releasing BIOS updates. The latest microcode is version 12B. If you update the BIOS and it does not include the latest microcode version, you can easily install this patch so it is applied to the CPU each time Windows boots up.

Just checked for bios updates for my laptop and I have the latest version which is dated 2024.9.10, also I had an Intel ME update installed in bios a couple of months ago and I still have version 11F, looks like I'll have to install it at windows level as you suggested. Thanks, I'll do that now.

Upd: I installed the patch without any problems, the version that was displayed in TS changed.

 

[turtlemark]

On my desktop platforms, setting the "CPU E Cache" offset makes no change on core voltage and power consumption, and undervolting it too much triggers an instant blue screen, so I never set it. I only set CPU Core and CPU P Cache offsets with same value.
I also tested on a 13700KF+Z790 platform with 125W power limit and microcode 0x129. Setting negative offset of "CPU E Cache" won't raise E core frequency or benchmark score (CB R23).
This item is related to "E Core L2 Cache" voltage in BIOS (MSI and ASRock). In my opinion, the "E Core (L2) Cache" voltage is just like SA voltage, fully controlled by FIVR, and doesn't affect the global core voltage.
The shifting of offset value is caused by Per-Core offset. I have posted a thread about this. It looks like the value read by TS is a "final value" that CPU picked based on core-parking.
I have been using TS on desktop platforms for years, from cometlake to raptorlake, and everything works as expected. So I think there is no significant difference between desktop and mobile platforms. For developing and debugging, I recommend using a 14600K+ASRock Z790 desktop platform. i9 is not necessary, since the so-called exclusive feature TVB is fully supported by i5 and i7.