TPL setting not working.

[Vicdeo]

Hello everyone, pardon me for my bad english as it is not my first language.

My laptop is an HP pavillion, 2018 model with an I5 8250U.
Before, my laptop was able to clock 3.4ghz @15W PL1 in games with 90c
I had used throttlestop for 2 months now, but since last week the TPL setting seems not to be working. PL2 warning sign showed even though the CPU was not using PL1 level.
I've also disable speedshift and set PL4 to 0 (read on other website this may help stop EDP other throttling). I have also set the power plan to high performance. MSR and MMIO value also seems to match. BD PROCHOT seems not to be the issue.
I am comfortable running my laptop on 90c as what I need is stable clock.
Can anyone tell me what I'm doing wrong? Or if intel has decided to block TPL changes, does anyone know a way to bypass it? Thank you.

 

[unclewebb]

but since last week

There might have been a BIOS update or a Windows 11 update that has broken your computer. It also could be a sensor of some sort that has failed and is now sending a signal to an embedded controller (EC) that is setting an ultra low power limit. The EC power limit cannot be controlled by using ThrottleStop.

When you undervolt, try using the same offset value for both the core and the cache. If you only undervolt the core it is probably not going to do anything.

Below where it says Unlock Adjustable Voltage, set that to Adaptive. Do not set this to Static. Move the slider all the way to the left. It should show the word Default in the voltage box. Set IccMax to the maximum, 255.75, for both the core and the cache.

In the TPL window, do not check Sync MMIO and do not check either of the Clamp boxes. Check the MMIO Lock box at the top right instead. Check the Short Power PL2 box and set the turbo time limit back to the default 28 second value.

I doubt any of these suggestions are going to solve your problem. If the EC decides it wants to enforce a low ball power limit for whatever reason, there is no easy way to fix that problem.