TSMC Reportedly Preparing New Equipment for 1.4 nm Trial Run at "P2" Baoshan Plant

[T0@st]

Industry insiders posit that TSMC's two flagship fabrication facilities are running ahead of schedule with the development of an advanced 2 nm (N2) process node. A cross-facility mass production phase is tipped to begin later this year, which leaves room for next-level experiments. Taiwan's Economic Daily News has heard supply chain whispers about the Baoshan "P2" plant making internal preparations for a truly cutting edge 1.4 nm-class product. According to the report, unnamed sources have claimed that: "TSMC has made a major breakthrough in the advancement of its 1.4 nm process. (The company) has recently notified suppliers to prepare the necessary equipment for 1.4 nm, and plans to install a trial production 'mini-line' at P2 (Baoshan Fab 20)."

Their Hsinchu-adjacent "Fab 20" site is touted as a leading player in the prototyping of this new technology. Industry moles reckon that "1.4 nm expertise" will eventually trickle over to nearby "P3 and P4 plants" for full production phases. Allegedly, these factories were originally going to be involved in the manufacturing of 2 nm (N2) wafers. Additionally, TSMC's "Fab 25" campus could potentially play host to trial 1.4 nm activities—the Economic Daily News article proposes that four plants based in the Central Taiwan Science Park are pitching in with collaborative work. As interpreted by TrendForce, "P1" could begin "risk trial production" by 2027, followed by full-scale output within the following year.



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[ThomasK]

No wonder Intel is thinking of going fabless. How do you even compete? 18A is barely working and your competitor is already moving on to something more advanced.

 

[Denver]

The entire smartphone, PC, datacenter and AI industry prays every day for TSMC to keep moving forward without the setbacks and stumbles that competitors face.

 

[londiste]

No wonder Intel is thinking of going fabless. How do you even compete? 18A is barely working and your competitor is already moving on to something more advanced.

There are arguments to be made/had about execution but Intel is running on a very similar if not pretty much the same roadmap. TSMC is talking about N2 mass production in second half of 2025, same as Intel with 18A, and these are by specs comparable nodes. TSMC has started work on 1.4nm as this story says, it's mass production ETA is somewhere in 2027 range. Again, Intel has 14A on their roadmap with ETA in 2027. Exactly the same goes with Samsung. And all three have been hitting some delays here and there, including TSMC.

 

[tfp]

Smart of them to skip the 1.8nm marketing name and going straight to 1.4nm. I can tell the results will be awesome.

 

[Denver]

There are arguments to be made/had about execution but Intel is running on a very similar if not pretty much the same roadmap. TSMC is talking about N2 mass production in second half of 2025, same as Intel with 18A, and these are by specs comparable nodes. TSMC has started work on 1.4nm as this story says, it's mass production ETA is somewhere in 2027 range. Again, Intel has 14A on their roadmap with ETA in 2027. Exactly the same goes with Samsung. And all three have been hitting some delays here and there, including TSMC.

Intel A18 is comparable to TSMC 3nm. 2nm is a whole new world, 31% denser right from the first generation. TSMC is known for releasing even more optimized PPA (Power, Performance, Area) process node interactions.

"Analysts at TechInsights believe that TSMC's N2 offers a high-density (HD) standard-cell transistor density of 313 MTr/mm^2, which far exceeds the HD cell density of Intel's 18A (238 MTr/mm^2) and Samsung's SF2/SF3P (231 MTr/mm^2)."

 

[bonehead123]

Progress is good, competition is good too (but almost non-existent), but....

gimme sub-sub nm or gimme death

You go, TSMC !

 

[Scrizz]

Intel A18 is comparable to TSMC 3nm. 2nm is a whole new world, 31% denser right from the first generation. TSMC is known for releasing even more optimized PPA (Power, Performance, Area) process node interactions.

"Analysts at TechInsights believe that TSMC's N2 offers a high-density (HD) standard-cell transistor density of 313 MTr/mm^2, which far exceeds the HD cell density of Intel's 18A (238 MTr/mm^2) and Samsung's SF2/SF3P (231 MTr/mm^2)."

aka BS

 

[Endymio]

Intel A18 is comparable to TSMC 3nm. 2nm is a whole new world, 31% denser right from the first generation.

TSMC is quoting quite different figures: -- only a 15% increase in density and performance over N3.

And to further put a damper on things, the per-wafer cost will rise 10% and design costs by even more, so the price-performance delta on N2 is going to be razor thin.

TSMC Details Its High-End "2nm Process", Revealing Massive Performance & Efficiency Improvements

TSMC has revealed additional details about its "2nm N2" technology, disclosing massive advancements in yield rates and performance metrics.

wccftech.com

 

[TumbleGeorge]

TSMC is quoting quite different figures: -- only a 15% increase in density and performance over N3

Yes but 15% are 31% in sick of enthusiasm eyes.

 

[Prima.Vera]

What does that 1.4nm means? Where is it measured TSMC? Please clarify.

 

[londiste]

What does that 1.4nm means? Where is it measured TSMC? Please clarify.

In marketing department? Not clear exactly what gets measured though

Intel A18 is comparable to TSMC 3nm. 2nm is a whole new world, 31% denser right from the first generation. TSMC is known for releasing even more optimized PPA (Power, Performance, Area) process node interactions.
"Analysts at TechInsights believe that TSMC's N2 offers a high-density (HD) standard-cell transistor density of 313 MTr/mm^2, which far exceeds the HD cell density of Intel's 18A (238 MTr/mm^2) and Samsung's SF2/SF3P (231 MTr/mm^2)."

Intel is trying but their HD libraries so far have not been the best (or the focus). Intel tends to focus much more on the HP variations. Intel 3 tends to be comparable to N4 for HD but to N3 for HP. By all indications this will continue with next generation of processes and both Intel's history as well as some of the new things - PowerVIA for example - point toward Intel's HP being much more competitive.

Edit:
Searched for where your quote is from and I do not seem to be far from what TechInsights said in more detail:

Intel vs. TSMC Process Nodes Battle: Speed or Density – Which Wins? - PaZimbabwe

TechInsights and SemiWiki recently unveiled significant insights into Intel and TSMC’s forthcoming 18A (1.8nm-class) and N2 (2nm-class) process technologies at the International Electronic Devices Meeting (IEDM). Reports from TechInsights suggest that Intel’s 18A technology could deliver...

www.pazimbabwe.com

 

[Endymio]

What does that 1.4nm means? Where is it measured TSMC? Please clarify.

Long, long ago it used to be average feature size, then minumum feature size. Now it's utterly meaningless. TSMS's "3 nm" node, for instance, has an average feature size closer to 34nm than to 3.

 

[rattlehead99]

What does that 1.4nm means? Where is it measured TSMC? Please clarify.

The names have been pure marketing for over a decade. The individual parts of the transistor are much bigger than the marketing name, let alone the entire transistor.

 

[Philaphlous]

Not an entire GPU/CPU/APU is built on a single node correct? Meaning the entire die isn't made with just 2/3nm tech.... I'm pretty sure some parts are like 6-8-12-14-28nm depending on where it is. It'll be interesting as time goes on, if these areas continue to shrink on the chip....performance should in theory continue to increase regardless if the smallest node doesn't decrease in size that much....

 

[Endymio]

Not an entire GPU/CPU/APU is built on a single node correct? Meaning the entire die isn't made with just 2/3nm tech.... I'm pretty sure some parts are like 6-8-12-14-28nm depending on where it is. It'll be interesting as time goes on, if these areas continue to shrink on the chip....performance should in theory continue to increase regardless if the smallest node doesn't decrease in size that much....

You may (?) be conflating two different factors here. Heterogeneous integration (i.e. "chiplets") usually involve producing die segments on older nodes to save costs, then interconnecting them. But even on a single die itself, logic is smaller than SRAM which is smaller than analog. These latter two have become nearly impossible to scale further for technical reasons. TSMC, for instance, got zero SRAM scaling on N3, and almost none on N5 (though I believe N2 managed to scale SRAM by the same margin as logic).

 

[Prima.Vera]

In marketing department? Not clear exactly what gets measured though

Long, long ago it used to be average feature size, then minumum feature size. Now it's utterly meaningless. TSMS's "3 nm" node, for instance, has an average feature size closer to 34nm than to 3.

The names have been pure marketing for over a decade. The individual parts of the transistor are much bigger than the marketing name, let alone the entire transistor.

In this case, what is stopping Intel or Samesuck to just wake up in the morning and say "Hey, we just started production on our 1.3 or 1.2nm nodes!! Please send us your billions! "
Is not like someone would check on them or call the scam....

 

[Denver]

TSMC is quoting quite different figures: -- only a 15% increase in density and performance over N3.

And to further put a damper on things, the per-wafer cost will rise 10% and design costs by even more, so the price-performance delta on N2 is going to be razor thin.

TSMC Details Its High-End "2nm Process", Revealing Massive Performance & Efficiency Improvements

TSMC has revealed additional details about its "2nm N2" technology, disclosing massive advancements in yield rates and performance metrics.

wccftech.com

Nope, in this statement, TSMC compared it to N3E with all its density optimizations in place, using ARM test chips designed for density rather than frequency. Meanwhile, even mobile chips prioritized clock speed over density, creating the misleading impression that the gains weren’t significant.

However, when we examine the specs, SRAM in N2 is 20% denser than in N3E. That alone already gives it an advantage over Intel’s A18, which has specs comparable to N3E. Don't forget that logic always shrinks much more than SRAM.

SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements | Tom's Hardware
IEDM 2022 – TSMC 3nm - SemiWiki

 

[Squared]

Not an entire GPU/CPU/APU is built on a single node correct? Meaning the entire die isn't made with just 2/3nm tech.... I'm pretty sure some parts are like 6-8-12-14-28nm depending on where it is. It'll be interesting as time goes on, if these areas continue to shrink on the chip....performance should in theory continue to increase regardless if the smallest node doesn't decrease in size that much....

In an integrated circuit (AKA microchip or silicon chip or die), every part has to be built on a single node or it's not an integrated circuit. The RX 9070 XT, RTX 5090, and Arc B580 are all GPUs made of a single integrated circuit. The graphics card may have other integrated circuits perhaps for power delivery but only all the compute work happens on the GPU. Also the Core i7 13900K, Ryzen AI 370, and Snapdragon X CPUs have a single integrated circuit. The Core Ultra 285K, Core Ultra 155H, Ryzen 9700X, and RX 7900 XTX all have multiple integrated circuits making up one CPU or GPU, but the oldest node in that list is TSMC N6.

 

[londiste]

In this case, what is stopping Intel or Samesuck to just wake up in the morning and say "Hey, we just started production on our 1.3 or 1.2nm nodes!! Please send us your billions! "
Is not like someone would check on them or call the scam....

Why do you think Intel renamed 10nm to 7, 7nm to 4 etc? And it is not even about who is right or wrong, it was about the alignment in the end.

Not an entire GPU/CPU/APU is built on a single node correct? Meaning the entire die isn't made with just 2/3nm tech.... I'm pretty sure some parts are like 6-8-12-14-28nm depending on where it is. It'll be interesting as time goes on, if these areas continue to shrink on the chip....performance should in theory continue to increase regardless if the smallest node doesn't decrease in size that much....

Yes and no. Historically the entire GPU/CPU/APU are built on single node.

Chiplet is the canonical implementation of the idea of using multiple nodes as they fit (plus the size/yield considerations) where each piece is produced on most suitable (or in reality, cheapest) process and later connected together.

The more interesting approach that seems to be taking hold is using the same process but different libraries on the same die. Basically building the parts you need to be fast with HP transistors and have the rest on HD with the density it provides. TSMC has offered it since N5 I believe and it does get used on N3. Others are at least capable of it as well.

 

[95Viper]

Let's stay on topic.
And stop the off-colored comments.

 

[GenericUsername2001]

In this case, what is stopping Intel or Samesuck to just wake up in the morning and say "Hey, we just started production on our 1.3 or 1.2nm nodes!! Please send us your billions! "
Is not like someone would check on them or call the scam....

The companies potentially buying wafers from Intel or Samsung are not going to care about marketing name of any given process, but instead will want full technical details to send to their engineering teams, who of course will be able to tell how good the actual process is for whatever sort of chip the design company wants fabbed. Said full technical details are required for chip designing teams to be able to make a useful chip. So yes, any potential buyer would be checking on them and simply not use the fab if the price/performance/yield is not good enough.

 

[tfp]

Maybe companies still seem to use Samsung and "they are the worst". Must be more than just tech specs involved.

 

[londiste]

Maybe companies still seem to use Samsung and "they are the worst". Must be more than just tech specs involved.

Of course. Samsung themselves build a lot of stuff in their foundries. And not every customer needs, wants or can afford the latest and greatest. Hell, Nvidia's Ampere was not that long ago

 

[Endymio]

Maybe companies still seem to use Samsung and "they are the worst". Must be more than just tech specs involved.

Do you drive a Bugatti Veyron and own a monitor-grade $150K stereo system? Why not?