Some of the sources don't seem to understand how memory buses work, and I'm surprised that no-one seems to have picked up on this. Some people probably have, but I've not seen any mention of it so far.
- 12 GB GDDR6
- 192-bit or 256-bit memory bus
If it's 12GB, it's 192 bit.
- 58 SM, 7424 cores, 320-bit memory, 16 GB VRAM, GDDR6 or GDDR6X
If it's a 320-bit bus, it's not 16GB. It would be 10GB.
If it's 16GB, it is 256-bit.
- Most likely Navi 12 without HBM2
You can't do that. Navi 12's memory controller and PHY are designed for HBM2, and are not compatible with GDDR6. Cryptomining is very bandwidth-sensitive, and profitability is heavily dependent on minimising power usage, so AMD would want to use HBM2 even if they had the option not to - it would be worth it, especially with GPU prices as inflated as they are at the moment. Navi 10 effectively
is "Navi 12 without HBM" (i.e. 40 RDNA1 CUs with GDDR6 instead of HBM2). If it's Navi 10, call it Navi 10. If it's Navi 12, it will use HBM2.
The bandwidth mismatch that results when you use memory chips of different sizes means Nvidia is not going to use a 4x1GB+4x2GB layout, which is what would be needed to fit 12GB onto a 256-bit bus. There was a huge backlash against Nvidia when they last tried something like this (with the GTX 970).
