AMD Quietly Disables Zen 4's Loop Buffer Feature Without Performance Penalty
AMD has silently disabled the loop buffer feature in its Zen 4 processor architecture through an AGESA microcode update. This development, first reported by the website Chips and Cheese, affects the entire Ryzen 7000 series processors and related EPYC models. The loop buffer, a power-optimization feature capable of storing 144 entries (72 per thread with SMT enabled), was implemented for the first time in AMD's Zen 4 architecture but has been notably absent from the newer Zen 5 design. The feature's primary function was to allow the processor's front end to power down while maintaining operational efficiency. The change was discovered when testing an ASRock B650 PG Lightning motherboard paired with a Ryzen 9 7950X3D processor. Hardware performance monitoring showed the loop buffer was active in BIOS version 1.21 (AGESA 1.0.0.6) but ceased to function after updating to BIOS 3.10 with AGESA 1.2.0.2a.
In a performance test conducted by Chips and Cheese, we learned that there is no significant impact from the feature's deactivation, suggesting the existing op cache provides sufficient bandwidth for optimal processor operation. AMD's architectural design has historically relied on its op cache for similar functionality. The feature appeared experimental, given the lack of documentation and the absence of programming guides for loop buffer optimization. Unlike competitors Intel and Arm, who have extensively documented their loop buffer implementations, AMD's approach appeared less developed. While the exact reasoning behind the deactivation remains unclear, disabling undocumented features is a step in the right direction, mainly as future Zen architecture iteration doesn't rely on a loop buffer, as seen with Zen 5.
In a performance test conducted by Chips and Cheese, we learned that there is no significant impact from the feature's deactivation, suggesting the existing op cache provides sufficient bandwidth for optimal processor operation. AMD's architectural design has historically relied on its op cache for similar functionality. The feature appeared experimental, given the lack of documentation and the absence of programming guides for loop buffer optimization. Unlike competitors Intel and Arm, who have extensively documented their loop buffer implementations, AMD's approach appeared less developed. While the exact reasoning behind the deactivation remains unclear, disabling undocumented features is a step in the right direction, mainly as future Zen architecture iteration doesn't rely on a loop buffer, as seen with Zen 5.
