Synopsys, Inc. today announced its continued, close collaboration with TSMC to deliver advanced EDA and IP solutions on TSMC's most advanced process and 3DFabric technologies to accelerate innovation for AI and multi-die designs. The relentless computational demands in AI applications require semiconductor technologies to keep pace. From an industry leading AI-driven EDA suite, powered by Synopsys.ai for enhanced productivity and silicon results to complete solutions that facilitate the migration to 2.5/3D multi-die architectures, Synopsys and TSMC have worked closely for decades to pave the path for the future of billion to trillion-transistor AI chip designs.

"TSMC is excited to collaborate with Synopsys to develop pioneering EDA and IP solutions tailored for the rigorous compute demands of AI designs on TSMC advanced process and 3DFabric technologies," said Dan Kochpatcharin, head of the Ecosystem and Alliance Management Division at TSMC. "The results of our latest collaboration across Synopsys' AI-driven EDA suite and silicon-proven IP have helped our mutual customers significantly enhance their productivity and deliver remarkable performance, power, and area results for advanced AI chip designs.

TSMC has reportedly initiated production of Apple's last-generation A16 Bionic processors at its newly constructed Fab 21 in Arizona. This development comes significantly earlier than anticipated, with the facility's full-scale production initially scheduled for 2025. According to insights from industry expert Tim Culpan, the Arizona plant is already churning out a modest but noteworthy quantity of A16 Bionic chips. These processors are being manufactured using TSMC's NP4 4 nm semiconductor node. Culpan also hinted at a substantial increase in production capacity once the second stage of Fab 21's initial phase becomes operational.

This early start serves a critical function for TSMC, allowing the company to calibrate its advanced equipment and refine its manufacturing processes thoroughly. Using the well-established A16 Bionic design, TSMC can ensure its new facility meets the exacting standards required for next-generation semiconductor production. The news aligns with recent industry buzz suggesting that Fab 21 is already achieving yield rates comparable to TSMC's long-established Taiwanese plants—a remarkable feat for a newly launched facility. While current output remains limited, this milestone marks a significant step in TSMC's expansion into US-based chip manufacturing. With more fabs on American soil, companies can push domestic manufacturing and ensure that geopolitics don't hinder the vital supply chain.

During the Semicon Taiwan 2024 summit event, TSMC VP of Advanced Packaging Technology, Jun He, spoke about the importance of merging AI chip memory and logic chips using 3D IC technology. He predicted that by 2030 the worldwide semiconductor industry would hit the $1 trillion milestone with HPC and AI leading 40 percent of the market share. In 2027, TSMC will introduce the 2.5D CoWoS technology that includes eight A16 process chipsets and 12 HBM4. AI processors that use this technology will not only be much cheaper to produce but will also provide engineers with a greater level of convenience. Engineers will have the option to write new codes into them instead. Manufacturers are cutting the SoC and HBM architectural conversion and mass production costs down to nearly one-fourth.

Nevertheless, the increasing production capacities of 3D IC technology remain the main challenge, as the size of chips and the complexity of manufacturing are decisive factors. However, the higher the size of the chips, the more chiplets are added, and thus the performance is improved, but this now makes the process even more complicated and is associated with more risks of misalignment, breakage, and extraction failure.

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

Apple today announced iPhone 15 and iPhone 15 Plus, featuring an industry-first color-infused back glass with a stunning, textured matte finish, and a new contoured edge on the aluminium enclosure. Both models feature the Dynamic Island, and an advanced camera system designed to help users take fantastic photos of everyday moments in their lives. A powerful 48MP Main camera enables super-high-resolution photos and a new 2x Telephoto option to give users a total of three optical zoom levels—like having a third camera. The iPhone 15 lineup also introduces the next generation of portraits, making it easier to capture portraits with great detail and low-light performance. Building on Apple's innovative satellite infrastructure, Roadside Assistance via satellite can connect users to AAA if they have car trouble while off the grid. With A16 Bionic for powerful, proven performance; a USB‑C connector; Precision Finding for Find My friends; and industry-leading durability features, iPhone 15 and iPhone 15 Plus represent a huge leap forward.

iPhone 15 and iPhone 15 Plus will be available in five stunning new colors: pink, yellow, green, blue, and black. Pre-orders begin Friday, September 15, with availability beginning Friday, September 22.

Samsung's unannounced Exynos 2400 mobile chipset has been linked to the upcoming Galaxy S24 smartphone family, but internet tipsters have speculated that the in-house SoC will be reserved for the baseline model only. The more expensive Plus and Ultra variants could be the main targets for flagship smartphone fetishists - it is possible that Qualcomm's upper echelon Snapdragon 8 Gen 3 chipset is set to feature within these premium devices. Samsung's Exynos processors are not considered to be fan favorites, but industry insiders reckon that the latest performance figures indicate that Samsung's up-and-comer has the potential to turn some heads. Exact specifications for the Exynos 2400 are not public knowledge - one of the tipsters suggests that a 10-core layout has been settled on by Samsung, as well as a recent bump up in GPU core count - from 6 to 12. The company's own 4 nm SF4P process is the apparent choice set for production line.

A leaker has posted benchmark scores generated by an unknown device that was running an Exynos 2400 SoC - the Geekbench 5 results indicate an average single-core score of 1530 with a peak of 1711. The multi-core average score is shown to be 6210, and the highest number achieved is 6967. Therefore the Exynos 2400 is 31% percent faster (in multi-core performance) than the refreshed Snapdragon 8 Gen 2 variant currently found in Galaxy S23 Ultra smartphones, but the divide between the two in terms of single-core performance is not so great. The 2400 manages to outpace (by 30%) Apple's present generation Bionic A16's average multi-core score, although the latter beats the presumed engineering sample's single-core result by 20%. The Exynos 2400 will face a new lineup of rival mobile processors in 2024 - namely Apple's next generation Bionic A17 and Qualcomm's Snapdragon 8 Gen 3, so it is difficult to extrapolate today's leaked figures into a future scenario.

Apple's engineering team is rumored to be adjusting performance targets set for its next generation mobile SoC - the A17 Bionic - due to issues at the TSMC foundry. The cutting edge 3 nm process is proving difficult to handle, according to industry tipsters on Twitter. The leaks point to the A17 Bionic's overall performance goals being lowered by 20%, mainly due to the TSMC N3B node not meeting production targets. The factory is apparently lowering its yield and execution targets due to ongoing problems with FinFET limitations.

The leakers have recently revealed more up-to-date A17 Bionic's Geekbench 6 scores, with single thread performance at 3019, and multi-thread at 7860. Various publications have been hyping the mobile SoC's single thread performance as matching that of desktop CPUs from Intel and AMD, more specifically 13th-gen Core i7 and 'high-end' Ryzen models. Naturally the A17 Bionic cannot compete with these CPUs in terms of multi-thread performance.