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Advantech Announces Edge & AI Solutions with 5th Gen AMD EPYC Embedded Series Processors

Advantech, a leading provider of edge computing and edge AI solutions, is pleased to announce their high-performance server and network appliances are now powered by the latest AMD EPYC Embedded 9005 Series processors. By leveraging these cutting-edge platforms, Advantech is driving edge computing and AI to new heights—making solutions ideal for 5G edge cloud, AI, machine learning, and enhanced data security.

"We are excited about the launch of Advantech's latest generation of innovative edge computing and AI solutions powered by AMD EPYC Embedded 9005 Series processors," said Amey Deosthali, Senior Director of embedded core markets at AMD. "Optimized for embedded markets, EPYC Embedded 9005 provides exceptional compute performance for edge AI applications while delivering enhanced IO capabilities, product longevity, and system resiliency."

AMD Launches the EPYC Embedded 9005 "Turin" Family of Server Processors

AMD today launched the EPYC Embedded 9005 line of server processors in the embedded form-factor. These are non-socketed variants of the EPYC 9005 "Turin" server processors. The chips are intended for servers and other enterprise applications where processor replacements or upgradability are not a consideration. The EPYC Embedded 9005 "Turin" are otherwise every bit similar to the regular socketed EPYC 9005 series. These chips are based on a BGA version of the "Turin" chiplet-based processor, and powered by the "Zen 5" microarchitecture. Besides the BGA package, the EPYC Embedded 9005 series comes with a few features relevant to its form-factor and target use-cases.

To begin with, the EPYC Embedded 9005 "Turin" series comes with NTB (non-transparent bridging), a technology that enables high-performance data transfer between two processor packages across different memory domains. NTB doesn't use Infinity Fabric or even CXL, but a regular PCI-Express 5.0 x16 connection. It isn't intended to provide cache coherence, but to absorb faults across various memory domains. Next up, the series supports DRAM flush for enhanced power-loss mitigation. Upon detecting a power loss, the processor immediately dumps memory onto NVMe storage, before the machine turns off. On restart, the BIOS copies this memory dump from the NVMe SSD back to DRAM. Thirdly, the processors in the series support dual SPI flash interfaces, which enables system architects to embed lightweight operating systems directly onto a 64 MB SPI flash ROM, besides the primary SPI flash that stores the system BIOS. This lightweight OS can act like a bootloader for operating systems in other local storage devices.
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Apr 15th, 2025 13:39 EDT change timezone

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