News Posts matching #Fusion

Return to Keyword Browsing

HyperTransport 3.1 Specifications Emerge, 45 nm AMD CPUs Support it

The HyperTransport Consortium released an updated specification, HT 3.1, that increases the base clock speed of the HyperTransport bus from its previous version 3.0 limit of 2600 MHz (5200 MT/s) to 3200 MHz (6400 MT/s). The upcoming 45nm processors will be given a host of architectural updates, one of them being a revised HT 3.1 system bus. Since AMD processors use a 32-bit wide HyperTransport link to the core logic, the aggregate bandwidth of the system but would be raised to 51.6 GB/s (25.8 GB/s in each direction).

This 10 GB/s increment is supposed to favour the upcoming AMD Fusion processors, where a graphics processor would be embedded into the CPU. That could also mean that the CPU could carry PCI-Express switches, effectively eradicating the northbridge. This would mean performance gains with the CPU communicating with PCI-E devices directly instead of through a northbridge-based PCI-E switch, much in the same way as integration of memory controllers five years ago helped AMD processors. It is expected that motherboard vendors have no problems implementing HT 3.1, the AMD 790GX and 790FX chipsets offer native support to HT 3.1 with 45 nm CPUs.

Details of the First Fusion Derivative Called 'Shrike' Surface

AMD Fusion, the latest buzzword in the industry, simply put is a complex chip called Accelerated Processing Unit (APU), with a dual-core CPU, graphics processor, a PCI-Express switch and a DDR3 memory controller all rolled into one. This level of integration helps reduce system-level latencies, thereby improving performance and more importantly, reducing overall power-consumption and heat output, bringing it into the ultra-low power niche. AMD claims performance increments scaling up to 20 per cent for the CPU and up to 35 per cent for the GPU. Its compact package allows manufacturers to use it in building less than 1 inch thick notebooks.

The platform codenamed 'Shrike' is the first implementation of this design methodology. This industry schematic shows the various components of it. Shrike is slated for a H2, 2009 release. While it's not aimed to compete directly with the Intel Centrino Atom or VIA Isiah, it could just become a competitive platform for portable computing. Shrike consists of an APU codenamed "Swift" that connects to an external southbridge chip.
Return to Keyword Browsing
May 21st, 2024 13:32 EDT change timezone

New Forum Posts

Popular Reviews

Controversial News Posts