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JEDEC Publishes DDR4 NVDIMM-P Bus Protocol Standard

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD304-4.01 DDR4 NVDIMM-P Bus Protocol. The JEDEC NVDIMM-P standard will enable the industry to create advanced memory solutions that benefit from the enhanced system performance and novel data availability offered by Persistent Memory devices. JESD304-4.01 DDR4 NVDIMM-P is available for download from the JEDEC website.

As demand for DRAM capacity and bandwidth continues to grow, Hybrid DIMM technologies such as NVDIMM-P provide an innovative method for attaching emerging Persistent Memory in computing systems. Combining the access speeds of DDR with the reliability and capacity of non-volatile memories gives design engineers a new approach to data management. Much more than a standard DIMM specification, NVDIMM-P provides a full transactional interface protocol compatible with standard DRAM DIMMs along with a firmware programming model for the modules. NVDIMM-P simultaneously maximizes both re-use and flexibility by minimizing system host changes, providing an interface of the lowest latency to emerging memory, and offering flexible support for varied Persistent Memory media characteristics and use cases.

JEDEC Says DDR5 Standard Development Rapidly Advancing: ETA, 2018

JEDEC Solid State Technology Association, responsible for creating the standards on which all of your versions of DDR memory are based upon, recently announced that development of the DDR5 memory standard is well underway, and in time for a 2018 release. The standards body said DDR5 memory will provide double the bandwidth and density versus current generation DDR4. along with delivering improved channel efficiency. Though considering the rate at which DDR4 prices have been increasing as of late, we really should fell a little uneasy at what this new memory standard's adoption will entail.

The current highest base clock that JEDEC allows in their DDR4 memory standard before "overclocking" takes over is DDR4-2400 - with timings ranging from 15~18 for the CAS latency, as well as tRCD, and tRP. And if, as JEDEC says, DDR5 is to be "twice as fast", that could imply that we could end up seeing DDR5-4800. Consider that for a moment: DDR4 kits today only go so far as DDR4-4266, and those are so few and far between that they'll cost you a singular kidney.
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