AMD's upcoming Instinct MI400 accelerator series, scheduled for 2026 introduction, is set to incorporate a new Multimedia IO Die (MID) architecture alongside significant compute density improvements. According to recent patches discovered in AMD-GFX mailing lists, the accelerator will feature a dual Active Interposer Die (AID) design, with each AID housing four Accelerated Compute Dies (XCDs)—doubling the XCD count per AID compared to the current MI300 series. Introducing dedicated Multimedia IO Dies is a new entry in AMD's accelerator design philosophy. Documentation reveals support for up to two MIDs, with each likely paired to an AID, suggesting a more specialized approach to multimedia processing and interface management.

Specifications from the Register Remapping Table (RRMT) implementation indicate sophisticated die-to-die communication pathways, with support for local and remote transactions across XCDs, AIDs, and the new MIDs. The system enables granular control over eight potential XCD configurations (XCD0 through XCD7), suggesting that AMD can scale compute up and down with SKUs. While AMD has yet to release detailed specifications for the MI400 series, separating multimedia functions into dedicated dies could optimize performance and power efficiency. As the 2026 launch window approaches, AMD will spend the remaining time refining the software stack and ROCm support for its next-generation accelerator based on UDNA architecture. Since designing an accelerator is a year-long effort from the physical implementation standpoint, we expect the Instinct MI400 design to be finalized by now. All left is silicon bring-up, software optimization, and mass production, likely at TSMC's facilities.

Noted technology tipster, Kepler L2, believes that the Sony Interactive Entertainment (SIE) engineering team has finalized the design of a PlayStation 6 (PS6) system-on-chip (SoC)—insider information was shared on the NeoGAF forum (a popular computer game discussion board) late last week. It would be natural to assume that Sony's gaming division is deep into the process of developing a follow-up to its PlayStation 5 home console, but Kepler L2's fresh revelation points to surprisingly advanced progress. Insider sources point to the PS6's chip design being: "complete and in pre-silicon validation already, with A0 tapeout scheduled for late this year."

Industry experts have analyzed PlayStation development cycles of days past—history has demonstrated a pattern of the A0 tapeout phase reaching completion around two years before the rollout of finalized products at retail. Kepler L2 reckons that this pattern will be repeated—indicating a possible launch of PlayStation by 2027. The rumored PS6 chipset has been linked to AMD's "gfx13" target—everyone's favorite Team Red tipster posits that Sony engineers are working with a "fork" of this next-gen "UDNA" graphics technology. The rumor mill has generated additional PS6 SoC-related internet chatter—last Friday, Chiphell alleged a possible adoption of Team Red's X3 V-cache technology.

AMD is rumored to be building its next-generation CCD (core complex die) that implements the "Zen 6" microarchitecture, on the 3 nm TSMC N3E foundry node. This is part of a set of rumors from ChipHell forum, which got past rumors on AMD right. Apparently, AMD will also refresh the I/O dies for its next generation process, building them on the 4 nm foundry node, likely the TSMC N4C. The TSMC N3E node offers a 20% speed improvement, over 30% power savings, and approximately 60% logic density increase over TSMC N5, whereas the TSMC N4P node that the company uses for its current "Zen 5" chiplets only clock minor increases in logic density and power over N5. The N3E node relies on EUV double-patterning to achieve its logic density increases.

Perhaps the most interesting piece of news is the new-generation I/O dies. AMD is building these on the 4 nm node, which is a significant step up from the 6 nm node its current I/O dies are built on. On the client side of things, 4 nm will enable AMD to give the new cIOD an updated iGPU, probably based on a newer graphics architecture, such as RDNA 3.5. It will also give AMD the opportunity to integrate an NPU. The company might also update its key I/O components, such as the DDR5 memory controllers, to support higher memory speeds unlocked by CUDIMMs. We don't predict any updates on the PCIe front, since AMD is expected to carry on with Socket AM5, which determines that the cIOD puts out 28 PCIe Gen 5 lanes. At best, the USB interface put out from the processor could be updated to USB4 through an on-die host controller. Over on the server side, the new-generation sIOD will bring much needed increases to the DDR5 memory speeds enabled by clock drivers.

While the current generation of AMD graphics cards employs RDNA 3 at its core, and the upcoming RX 8000 series will feature RDNA 4, the latest leaks suggest RDNA 5 is not in development. Instead, UDNA will succeed RDNA 4, simplifying AMD's GPU roadmap. A credible source on the Chiphell forums, zhangzhonghao, reports that the UDNA-based RX 9000 series and Instinct MI400 AI accelerator will incorporate the same advanced Arithmetic Logic Unit (ALU) designs in both products, reminiscent of AMD's earlier GCN architectures before the CDNA and RDNA split. Sony's next-generation PlayStation 6 is also rumored to adopt UDNA technology. The PS5 and PS5 Pro currently utilize RDNA 2, while the Pro variant integrates elements of RDNA 4 for enhanced ray tracing. The PS6's CPU configuration remains unclear, but speculation revolves around Zen 4 or Zen 5 architectures.

The first UDNA gaming GPUs are expected to enter production by Q2 2026. Interestingly, AMD's RDNA 4 GPUs are anticipated to focus on entry-level to mid-range markets, potentially leaving high-end offerings until the UDNA generation. This strategic pause may allow AMD to refine AI-accelerated technologies like FidelityFX Super Resolution (FSR) 4, aiming to compete with NVIDIA's DLSS. This unification is inspired by NVIDIA's CUDA ecosystem, which supports cross-platform compatibility from laptops to high-performance servers. As AMD sees it, the decision addresses the challenges posed by maintaining separate architectures, which complicate memory subsystem optimizations and hinder forward and backward compatibility. Putting developer resources into RDNA 5 is not economically or strategically wise, given that UDNA is about to take over. Additionally, the company is enabling ROCm software support across all products ranging from consumer Radeon to enterprise Instinct MI. Accelerating software for one platform will translate to the entire product stack.

A few days ago, we reported on AMD's newest expansion plans for Serbia. The company opened two new engineering design centers with offices in Belgrade and Nis. We were invited to join the opening ceremony and got an exclusive interview with one of AMD's top executives, Andrej Zdravkovic, who is the senior vice president and Chief Software Officer. Previously, we reported on AMD's transition to become a software company. The company has recently tripled its software engineering workforce and is moving some of its best people to support these teams. AMD's plan is spread over a three to five-year timeframe to improve its software ecosystem, accelerating hardware development to launch new products more frequently and to react to changes in software demand. AMD found that to help these expansion efforts, opening new design centers in Serbia would be very advantageous.

We sat down with Andrej Zdravkovic to discuss the purpose of AMD's establishment in Serbia and the future of some products. Zdravkovic is actually an engineer from Serbia, where he completed his Bachelor's and Master's degrees in electrical engineering from Belgrade University. In 1998, Zdravkovic joined ATI and quickly rose through the ranks, eventually becoming a senior director. During his decade-long tenure, Zdravkovic witnessed a significant industry shift as AMD acquired ATI in 2006. After a brief stint at another company, Zdravkovic returned to AMD in 2015, bringing with him a wealth of experience and a unique perspective on the evolution of the graphics and computing industry.Here is the full interview: