Tuesday, May 15th 2012
AMD Selects Synopsys as a Verification IP Partner
Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SoC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM AMBA AXI interconnect, SATA 3.0, PCI Express Gen 3, and MIPI, as well as Synopsys' Protocol Analyzer, a unique protocol-aware SoC debug environment.
"In our verification environment for Southbridge SoCs and IP cores, we utilize several interfaces, including AXI3 and USB 3.0. After an extensive evaluation, we selected Synopsys' next-generation Discovery VIP for several of our leading SoC designs," said Thomas Bodmer, manager of design engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys' Protocol Analyzer technology to narrow down protocol violations and debug the root causes."
The growing use of increasingly complex interface protocols makes verification and debug of SoCs one of the most difficult and time-consuming aspects of functional verification. VIP provides functional models that engineers use to test all SoC interfaces before manufacturing, enabling them to verify whether an interface conforms to published specification. Synopsys' Discovery VIP family offers up to four times (4X) higher performance than other commercial VIP, as well as ease-of-use, ease-of-debug, configuration, coverage and test-development capabilities to improve SoC verification productivity.
"The strategic agreement announced today expands and accelerates the successful long-standing verification collaboration between AMD and Synopsys," said Manoj Gandhi, senior vice president and general manager of the Synopsys Verification Group. "With the increasingly critical nature of VIP in SoC verification, we continue to collaborate with AMD to deliver leading VIP technology that helps manage the total cost of verification."
"In our verification environment for Southbridge SoCs and IP cores, we utilize several interfaces, including AXI3 and USB 3.0. After an extensive evaluation, we selected Synopsys' next-generation Discovery VIP for several of our leading SoC designs," said Thomas Bodmer, manager of design engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys' Protocol Analyzer technology to narrow down protocol violations and debug the root causes."
The growing use of increasingly complex interface protocols makes verification and debug of SoCs one of the most difficult and time-consuming aspects of functional verification. VIP provides functional models that engineers use to test all SoC interfaces before manufacturing, enabling them to verify whether an interface conforms to published specification. Synopsys' Discovery VIP family offers up to four times (4X) higher performance than other commercial VIP, as well as ease-of-use, ease-of-debug, configuration, coverage and test-development capabilities to improve SoC verification productivity.
"The strategic agreement announced today expands and accelerates the successful long-standing verification collaboration between AMD and Synopsys," said Manoj Gandhi, senior vice president and general manager of the Synopsys Verification Group. "With the increasingly critical nature of VIP in SoC verification, we continue to collaborate with AMD to deliver leading VIP technology that helps manage the total cost of verification."
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