Samsung isn't the only Korean memory giant showing off its latest tech at the upcoming IEEE Solid State Circuit Conference (SSCC) in February, 2024; it will be joined by SK Hynix, which will demo competing tech across both its volatile and non-volatile memory lines. To begin with, SK Hynix will be the second company to show off a GDDR7 memory chip, after Samsung. The SK Hynix chip is capable of 35.4 Gbps speeds, which is lower than the 37 Gbps Samsung is showing off, but at the same 16 Gbit density. This density allows the deployment of 16 GB of video memory across a 256-bit memory bus. Not all next-generation GPUs will max out 37 Gbps, some may run at lower memory speeds, and they have suitable options in the SK Hynix product stack. Much like Samsung, SK Hynix is implementing PAM3 I/O signaling, and a proprietary low-power architecture (though the company wouldn't elaborate on whether it's similar to the four low-speed clock states as the Samsung chips).

GDDR7 is bound to dominate the next generation of graphics cards across the gaming and pro-vis segments; however the AI HPC processor market will continue to bank heavily on HBM3E. SK Hynix has innovated here, and will show off a new 16-high 48 GB (384 Gbit) HBM3E stack design that's capable of 1280 GB/s over a single stack. A processor with even four such stacks will have 192 GB of memory at 5.12 TB/s of bandwidth. The stack implements a new all-around power TSV (through silicon via) design, and a 6-phase RDQS (read data queue strobe) scheme, for TSV area optimization. Lastly, the SK Hynix sessions will also include the first demo of its ambitious LPDDR5T (LPDDR5 Turbo) memory standard aimed at smartphones, tablets, and thin-and-light notebooks. This chip achieves a data-rate of 10.5 Gb/s per pin, and a DRAM voltage of 1.05 V. Such high data speeds are possible thanks to a proprietary parasitic capacitance reduction technology, and a voltage offset calibrated receiver tech.