UPDATE: Some slides have surfaced today on Reddit that actually place Intel's updated 10 nm roadmap as starting initial risk production in 2Q 2018. The same leaks also point towards a yearly advancement in process technology (akin to Intel's current 14 nm+ and 14 nm++ production processes), with 10 nm+ risk production on 1Q 2019 and 10 nm++ on 1Q 2020. This roadmap, however, is relative to Intel's Custom Foundry partners; as such, this doesn't go directly against Intel CEO's Brian Kzarnich remarks on the latest investor call, since he was likely talking about the 10 nm ramp-up on Intel's own products.

Intel CEO Brian Krzanich has come out to say that the company's first 10 nm CPUs based on the "Cannon Lake" micro-architecture will see the light of day before this year's end. Intel has been having a slew of ramp-up delays with its 10 nm products, which prompted a slippage from an expected 2016, full-scale launch (whose ship has sailed, clearly) towards a timed, product-tier based strategy. Intel opted to first introduce 10 nm technology to FPGA accelerators, which due to their redundancy, would suffer less from yield issues.

Non-volatile memory often has the first pick of a new silicon fabrication process, as it is a low-risk development. A NAND flash chip is essentially a sea of transistors, with a fraction of R&D cost of something as specialized as a CPU die. It should come as no surprise, then, that the first chips to be built on Intel's swanky new 10 nanometer fabs will be a 64-layer 3D NAND flash memory, the first of its kind for data center applications.

With its 10 nm process, Intel is introducing FinFET Hyper Scaling, Intel will increase transistor densities by 2.7 times over the kind of densities one would traditionally expect from 10 nm. This lets the company scale up NAND flash storage densities by just that much more. The first 10 nm 64-layer 3D NAND flash chips will have high data densities, while at the same time, Intel will be able to push low volumes, characteristic of a new process. This explains why the first SSDs built with these chips are targeted at data-centers, so fairly expensive, high-capacity SSDs can be pushed to customers that can afford them.

Intel is undoubtedly at the forefront of silicon processing technology these days, and has been for a long time. Being a fully integrated company from the bottom up, through the design and actual production of its silicon semiconductors, really does have a way of either paying of tremendously (as has been the case with Intel), or not at all (as was the case with AMD). That fabrication processes' nm ratings don't mean much in thhe industry right now has been the case for a while now; different companies use different calculations towards achieving a 22 nm or 14 nm claim, with some components in the same nm process having almost double the size of the same components in a competitor's equivalent. Intel has always been one of the more adamant defenders of an industry-wide categorization, both to avoid confusion and - naturally - put into perspective their process leadership.

A pretty underwhelming post on Intel's official page has pulled the curtains of the company's architecture name post their 8th generation processors. Actually, it's a little more puzzling than that, since Intel is actually detailing the codename of an architecture that's supposed to come right after their 8th generation - read, Coffee Lake - processors. Keep in mind that Coffee Lake, whilst being supposed to bring a reorganization of Intel's product stack in response to AMD's Ryzen success, will still be in the 14 nm++ process - the third such architecture in the same process, after Skylake (14 nm) and Kaby Lake (14 nm+) before it. Cannon Lake, however, is supposed to be the company's first tick into the 10 nm process.

Intel has moved over from their famed tick-tock (where tick is a process shrink and tock is a new architecture on the same process) cadence, and are now telling customers to expect at least three "tocks" per process. It's expected that Intel will launch mobile processors on the 10 nm process before any desktop parts are launched on the same process; this could stem from the fact that mobile parts are typically lower-power, smaller-sized dies, which are easier and cheaper to produce out of a still maturing 10 nm process, which usually implies lower than ideal yields.

After the absence of some further details on Intel's upcoming Coffee Lake mainstream CPU architecture (which is understandable, really, considering how the X299 platform and accompanying processors are all the rage these days), some new details have emerged. Intel's Coffee Lake architecture will still be manufactured on the company's 14 nm process, but is supposedly the last redoubt of the process, with Intel advancing to a 10 nm design with subsequent Cannon Lake.

The part in question is a six-core processor, which appears identified as a Genuine Intel CPU 0000 (so, an engineering sample.) SiSoft Sandra identifies the processor as a Kaby Lake-S part, which is probably because Coffee Lake processors aren't yet supported. The details show us a 3.1 GHz base, and a 4.2 GHz boost clock, with a 256 Kb L2 cache per core and a total of 12 MB L3 (so, 2 MB per core, which is in-line with current Kaby Lake offerings.) The 6-core "Coffee Lake" silicon will be built on a highly-refined 14 nm node by Intel, with a die-size of 149 mm². Quad-core parts won't be carved out of this silicon by disabling two cores, but rather be built on a smaller 126 mm² die.

Intel announced that its first CPU micro-architecture built on its upcoming 10 nanometer silicon fab process, the 9th generation Core "Cannon Lake," is on track. In a tweet on the official company account, Intel also announced that its second micro-architecture on the new 10 nm process, codenamed "Ice Lake," is taped out.

In the wake of a competitive CPU lineup by AMD, Intel is frantically upgrading its product lineup, beginning with the new "Basin Falls" HEDT platform early-Summer 2017, followed by its 14 nm "Coffee Lake" 8th generation Core series late-Summer. "Coffee Lake" sees the first six-core SKUs to Intel's mainstream desktop lineup, which has until now, been restricted to dual-core and quad-core parts.

AMD co-founder Jerry Sanders, in 2009 was famously quoted as stating that "real men have fabs," a jibe probably targeted at the budding fab-less CPU designers of the time. Years later, AMD spun-off its silicon fabrication business, which with a substantial investment of the Abu Dhabi government through its state-owned Advanced Technology Investment Company (ATIC), became GlobalFoundries (or GloFo in some vernacular). This company built strategic partnerships with the right players in the industry, acquisitions such as IBM's fabs, and is now at the forefront of sub-10 nm fab development. It remained one of AMD's biggest foundry partners besides TSMC and Samsung, and is manufacturing its AMD processors at a brand new facility in Upstate New York, USA.

AMD, on the other hand, doesn't regret spinning off GloFo. Speaking at Merrill Lynch Global Technology and Investment Conference, CTO Mark Papermaster said, that going fab-less has helped AMD focus on chip-design without worrying about manufacturing. Production is no longer a bottleneck for AMD, as it can now put out manufacturing contracts to a wider variety of foundry partners. Its chip-designers aren't limited by the constraints of an in-house fab, and can instead ask external fabs to optimize their nodes for their chip-designs, Papermaster said. 14 nm FinFET has added a level of standardization to the foundry industry.

Samsung stands as a technology giant in the industry, with tendrils stretching out towards almost every conceivable area of consumer, prosumer, and professional markets. It is also one of the companies which can actually bring up the fight to Intel when it comes to semiconductor manufacturing, with some analysts predicting the South Korean will dethrone Intel as the top chipmaker in Q2 of this year. Samsung scales from hyper-scale data centers to the internet-of-things, and is set to lead the industry with 8nm, 7nm, 6nm, 5nm, 4nm and 18nm FD-SOI in its newest process technology roadmap. The new Samsung roadmap shows how committed the company is (and the industry with it) towards enabling the highest performance possible from the depleting potential of the silicon medium. The 4 nm "post FinFET" structure process is set to be in risk production by 2020.

This announcement also marks Samsung's reiteration on the usage of EUV (Extreme Ultra Violet) tech towards wafer manufacturing, a technology that has long been hailed as the savior of denser processes, but has been ultimately pushed out of market adoption due to its complexity. Kelvin Low, senior director of foundry marketing at Samsung, said that the "magic number" for productivity (as in, with a sustainable investment/return ratio) with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, announced today that its second generation 10-nanometer (nm) FinFET process technology, 10LPP (Low Power Plus), has been qualified and is ready for production. With further enhancement in 3D FinFET structure, 10LPP allows up to 10-percent higher performance or 15-percent lower power consumption compared to the first generation 10LPE (Low-Power Early) process with the same area scaling.

Samsung was the first in the industry to begin mass production of system-on-chips (SoCs) products on 10LPE last October. The latest Samsung Galaxy S8 smartphones are powered by some of these SoCs. To meet long-term demand for the 10nm process for a wide range of customers, Samsung has started installing production equipment at its newest S3-line in Hwaseong, Korea. The S3-line is expected to be ready for production by the fourth quarter of this year.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced that it has commenced mass production of System-on-Chip (SoC) products with 10-nanometer (nm) FinFET technology for which would make it first in the industry. Following the successful mass production of the industry's first FinFET mobile application processor (AP) in January, 2015, Samsung extends its leadership in delivering leading-edge process technology to the mass market with the latest offering.

"The industry's first mass production of 10 nm FinFET technology demonstrates our leadership in advanced process technology," said Jong Shik Yoon, Executive Vice President, Head of Foundry Business at Samsung Electronics. "We will continue our efforts to innovate scaling technologies and provide differentiated total solutions to our customers."

Intel's silicon fabrication has evidently hit a huge roadblock. It turns out that not just "Kaby Lake," but its two successors "Cannon Lake" and "Coffee Lake" could also be built on the 14 nm node, at best with a few process-level improvements. "Coffee Lake" is the company's 9th generation Core architecture, which is two steps ahead of even the "Kaby Lake" architecture, which is due later this year. "Kaby Lake" makes its way to the 45W mobile (H-segment) and 15W mobile (U-segment), in Q4-2016 and Q3-2016, respectively. The 15W U-segment will be augmented by "Cannon Lake" (8th generation Core) in Q4-2017. By mid-2018, Intel plans to launch "Coffee Lake" across both H- and U-segments.

According to a "Hot Hardware" report, based on a job listing for a systems engineer at the company, Intel could be staring at the scary prospect of holding out on 14 nm for the next three years, only to be relieved by the stopgap 10 nm node, which makes its debut with the 10th generation Core "Tiger Lake" architecture, due for 2019. "Tiger Lake," its succeeding "Ice Lake," and one other architecture could be launched on 10 nm, before finally deploying 7 nm around 2022.

Silicon fabrication company GlobalFoundries is reportedly planning to skip development of the 10 nanometer (nm) process, and is aiming to jump straight to 7 nm. The company currently operates a 14 nm FinFET node. In 2015 the company acquired semiconductor manufacturing assets from IBM, and is using them to fast-track its development. When it's ready, the 7 nm node will offer both optical and EUV (extreme ultra-violet) lithography. Driving the EUV product is an IBM 3300 EUV fabricator at the company's advanced patterning center, in its Albany, New York fab.

Intel is opening up its silicon manufacturing facilities to fabless chip-makers, beginning with the manufacture of ARM SoCs. The company entered a licensing deal with ARM that allows ARM SoC designers such as Qualcomm, Apple, and Samsung, to manufacture their SoCs at Intel fabs. Intel is among the first fabs with a working 14 nm node, and is on-track for sub-10 nm node development.

Intel had a crack at the market segments typically addressed by ARM SoCs, with its own x86 chips, which failed to see the kind of volumes ARM chipmakers were pushing. The company has now changed tactics to open its fabs up to those ARM SoC makers, letting them manufacture their designs on proven silicon-fabrication tech, in geographically important locations. Intel has its cutting-edge fabs located in Costa Rica and Malaysia.

Taiwan's premier semiconductor foundry TSMC could begin 7 nanometer (nm) trial production in as early as the first half of 2017. Co-CEO Mark Liu, speaking at the company's investor-meet held earlier this month, stated that TSMC is currently engaging with over 20 companies on 7 nm development, with over 15 tape-outs within 2017, leading up to volume-production by early-2018. In the run-up to 7 nm, the company is also developing a 10 nm node for lower-powered devices (eg: mobile baseband). The company has already begun tape-outs of 10 nm chips in Q1-2016. TSMC is currently handling volume-production of 16 nm FinFET Plus chips.

With Intel's "tick-tock" product development cycle slowing down to a 3-launch cadence per silicon fab process, the company is preparing to launch no less than three micro-architectures on its next 10 nanometer silicon fab process. The first 10 nm CPU by Intel will launch in 2017.

In 2016, Intel will launch its 7th generation Core "Kaby Lake" processor, its third chip on the 14 nm process (after "Broadwell" and "Skylake"). The first 10 nm micro-architecture will be codenamed "Cannonlake," and will launch some time in 2017. Intel will build chips on the 10 nm for two more generations after "Cannonlake." The company's 2018 micro-architecture, built on the 10 nm will be codenamed "Icelake," and its 2019 release will be codenamed "Tigerlake." It's only 2020 that the company will pull out its next silicon fab process, 5 nm.

It has been confirmed that Samsung will be AMD's foundry partner for its next generation GPUs. It has been reported that AMD's upcoming "Arctic Islands" family of GPUs could be built on the 14 nanometer FinFET LPP (low-power Plus) process. AMD's rival NVIDIA, meanwhile, is building its next-gen "Pascal" GPU family on 16 nanometer FinFET node, likely at its traditional foundry partner TSMC.

It gets better - not only will Samsung manufacture AMD's next-gen GPUs, but also its upcoming "Zen" family of CPUs, at least a portion of it. AMD is looking to distribute manufacturing loads between two foundries, Samsung and GlobalFoundries, perhaps to ensure that foundry-level teething trouble doesn't throw its product launch cycle off the rails. One of the most talked about "Arctic Islands" GPUs is codenamed "Greenland," likely a successor to "Fiji." Sales of some of the first chips - GPUs or CPUs - made at Samsung, will begin some time in Q3 2016. Some of the other clients for Samsung's 14 nm FinFET node are Apple and Qualcomm. The company plans to speed up development of its more advanced 10 nm node to some time in 2017.

Semiconductor foundry TSMC assured its clients that the company will be ready with a 10 nanometer manufacturing node for volume production, by the 4th quarter of 2016. Company president and joint-CEO Mark Liu made this announcement during the company's recent Q2-2015 earnings call. "The recent progress of our 10 nanometer technology development is very encouraging and on track with our plan," he said. With volume production of chips commencing in Q4, some of the first products based on them should begin appearing in early-2017. "We ramp up 10 nm in the Q4 2016 next year, but the real product shipment will be in Q1 2017," said C.C. Wei, co-CEO.

Intel co-founder Gordon Moore's claim that transistor counts in microprocessors can be doubled with 2 years, by means of miniaturizing silicon lithography is beginning to buckle. In its latest earnings release, CEO Brian Krzanich said that the company's recent product cycles marked a slowing down of its "tick-tock" product development from 2 years to close to 2.5 years. With the company approaching sub-10 nm scales, it's bound to stay that way.

To keep Moore's Law alive, Intel adopted a product development strategy it calls tick-tock. Think of it as a metronome that give rhythm to the company. Each "tock" marks the arrival of a new micro-architecture, and each "tick" marks its miniaturization to a smaller silicon fab process. Normally, each year is bound to see one of the two in alternation.

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced today that it has begun mass producing a 128-gigabit (Gb), 3-bit multi-level-cell (MLC) NAND memory chip using 10 nanometer (nm)-class process technology this month. The highly advanced chip will enable high-density memory solutions such as embedded NAND storage and solid state drives (SSDs).

"By introducing next-generation memory storage products like the 128Gb NAND chip, Samsung is extremely well situated to meet growing global customer needs," said Young-Hyun Jun, executive vice president, memory sales & marketing, Device Solutions Division, Samsung Electronics. "The new chip is a critical product in the evolution of NAND flash, one whose timely production will enable us to increase our competitiveness in the high density memory storage market."

Intel will be capable making chips on the 14 nanometer silicon fabrication process, in 18-inch diameter wafers, "in two years," as development of the technology and machinery to make it happen is making good progress, according to company CTO Justin Rattner. He noted that Intel's aggressive tech advancement will keep Moore's Law relevant for at least the next 10 years. By the end of 2013, Intel's D1X Fab in Oregon, Fab 42 in Arizona, in the US, and Fab 24 in Ireland will begin producing batches of simple chips such as P1272 and P1273 series SoCs. After 14 nm, development for 10 nm, 7 nm, and 5 nm will follow, in order.

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today announced a next-generation 64 GB embedded multimedia card (eMMC) using 10 nanometer (nm)-class process technology. The new 64 Gb NAND memory went into production late last month.

Myungho Kim, vice president of Memory marketing, Device Solutions, Samsung Electronics noted, "The new high-speed, small form factor eMMC reinforces Samsung's technology leadership in storage memory solutions. We look forward to expanding our line-up of embedded memory solutions in conjunction with the new chip's design, in pursuing a system-level adoption of application processors and other key components that form the foundation for the most advanced mobile platforms. This will allow us to better attend to time-to-market demands enabling the design of more convenient features for next-generation mobile applications."