NVIDIA is reported to be cutting down on production of its highly popular RTX 2060 graphics card, in a bid to increase production of the RTX 30-series graphics cards that still elude most consumers looking to get one on their gaming rig. The decision may be motivated by increased margins on RTX 30-series products, as well as by the continuing component shortage in the industry, with even GDDR6 becoming a limiting factor to production capability.

While one might consider this a strange move at face value (Turing is manufactured on TSMC's 12 nm node, whilst Ampere is manufactured on Samsung's 8 nm), the fact of the matter is that there are a multitude of components required for GPUs besides the graphics processing silicon proper; and NVIDIA essentially sells ready-to-produce kits to AICs (Add-in-Card Partners) which already include all the required components, circuitry, and GPU slice to put together. And since supply on most components and even simple logic is currently strained, every component in an RTX 2060-allocated kit could be eating into final production capacity for the RTX 30-series graphics cards - hence the decision to curb the attempt to satiate pent-up demand with a last-generation graphics card and instead focusing on current-gen hardware.

IBM today unveiled a breakthrough in semiconductor design and process with the development of the world's first chip announced with 2 nanometer (nm) nanosheet technology. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

Demand for increased chip performance and energy efficiency continues to rise, especially in the era of hybrid cloud, AI, and the Internet of Things. IBM's new 2 nm chip technology helps advance the state-of-the-art in the semiconductor industry, addressing this growing demand. It is projected to achieve 45 percent higher performance, or 75 percent lower energy use, than today's most advanced 7 nm node chips.

European Union has today processed a declaration that was signed by 17 member states about the development of a 2 nm semiconductor node and an advanced low-power processor. The declaration signed today proposes that the EU puts away 145 billion Euros for the development of the technologies needed to manufacture a 2 nm semiconductor manufacturing process, along with the development of a custom, low-power embedded processor designed for industrial applications. The 17 member countries include Belgium, France, Germany, Croatia, Estonia, Italy, Greece, Malta, Spain, The Netherlands, Portugal, Austria, Slovenia, Slovakia, Romania, Finland, and Cyprus. All of the countries listed are going to join the development of these technologies and will have the funds to do it over the next 2-3 years.

EU DeclarationTo ensure Europe's technology sovereignty and competitiveness, as well as our capacity to address key environmental and societal challenges and new emerging mass markets, we need to strengthen Europe's capacity to develop the next generation of processors and semiconductors. This includes chips and embedded systems that offer the best performance for specific applications across a wide range of sectors as well as leading-edge manufacturing progressively advancing towards 2 nm nodes for processor technology. Using connectivity, where Europe enjoys global lead, as a major use case driver for developing such capacity enables Europe to set the right level of ambition. This will require a collective effort to pool investment and to coordinate actions, by both public and private stakeholders.

The Taiwan Economic Daily claims that TSMC has achieved a major internal breakthrough for the eventual rollout of 2 nm fabrication process technology. According to the publication, this breakthrough has turned TSMC even more optimistic towards a 2023 rollout of 2 nm risk production - which is all the more impressive considering reports that TSMC will be leaving the FinFet realm for a new multi-bridge channel field effect transistor (MBCFET) architecture - itself based on the Gate-All-Around (GAA) technology. This breakthrough comes one year after TSMC put together an internal team whose aim was to pave the way for 2 nm deployment.

MBCFET expands on the GAAFET architecture by taking the Nanowire field-effect transistor and expanding it so that it becomes a Nanosheet. The main idea is to make the field-effect transistor three-dimensional. This new complementary metal oxide semiconductor transistor can improve circuit control and reduce leakage current. This design philosophy is not exclusive to TSMC - Samsung has plans to deploy a variant of this design on their 3 nm process technology. And as has been the norm, further reductions in chip fabrication scale come at hefty costs - while the development cost for 5 nm has already achieved $476M in cost, Samsung reports that their 3 nm GAA technology will cost in excess of $500M - and 2 nm, naturally, will come in even costlier than that.

TSMC, the leading semiconductor foundry in the world, has reportedly begun construction of its 2 nm manufacturing facility. According to a DigiTimes report, translated by @chiakokhua on Twitter, besides the construction of 2 nm R&D center, TSMC has also started the construction of the manufacturing facility for that node, so it will be ready in time. Please do note that the node name doesn't represent the size of the transistor, so it will not actually be 2 nm wide. The new facilities will be located near TSMC's headquarters in Hsinchu Science Park, Taiwan. The report also confirms the first details about the node, specifically that it will use Gate-All-Around (GAA) technology. And there is also another interesting piece of information regarding even smaller node, the planning for 1 nm node has begun according to the source.

Besides advanced nodes, TSMC also laid out clear plans to accelerate the push of advanced packaging technology. That includes SoIC, InFO, CoWoS, and WoW. All of these technologies are classified as "3D Fabric" by the company, even though some are 2.5D. These technologies will be mass-produced at "ZhuNan" and "NanKe" facilities starting in the second half of 2021, and are expected to significantly contribute to the company's profits. It is also reported that the competing foundry, Samsung, has a 3D packaging technology of its own called X-cube, however, it is attracting customers a lot slower than TSMC due to the high costs of the new technology.

TSMC, the world's leading semiconductor manufacturing company, has reportedly started to accelerate research and development (R&D) of its next-generation 2 nm node. Having just recently announced that they will be starting production of a 5 nm process in Q4 of 2020, TSMC is pumping out nodes very fast and much faster compared to competition like Intel and Samsung. Having an R&D budget of almost 16 billion USD, TSMC seems to be spending the funds very wisely. The 5 nm node is going into volume production this year, and smaller nodes are already being prepared.

The 3 nm node is going into trial production in the first half of 2021, while the mass production is supposed to commence in 2022. As far as the 2 nm node, TSMC has recently purchased more expensive Extreme Ultra-Violet (EUV) lithography machines for the 2 nm node. Due to the high costs of these EUV machines, TSMC's capital spending will not be revisited this year and it should remain in the $16 billion range. As far as a timeline for 2 nm is concerned, we don't know when will TSMC start trial production as the node is still in development phases.

A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.

After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans