JEDEC Publishes Release 6 of the DDR3 SPD Standard
JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of Release 6 of the DDR3 Serial Presence Detect (SPD) document. The updated standard, SPD4_01_02_11: SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules (Release 6), describes new memory timing parameters and enables higher capacity memory modules, and may be downloaded free of charge from the JEDEC website.
"The DDR3 memory module market is in its full stride, with new applications pushing the technology into an ever-widening array of offerings, and the Serial Presence Detect is a reliable and consistent way to document the features of these new modules so that system software can tune system performance," said Mian Quddus, Chairman of JEDEC's JC-45 Committee for Dynamic Random Access Memory (DRAM) Modules. He added, "This release of the DDR3 SPD standard adds support for memory modules with up to 8 ranks of DDR3 SDRAMs, enabling 64GB per slot using mainstream 4Gb memory chips."
"The DDR3 memory module market is in its full stride, with new applications pushing the technology into an ever-widening array of offerings, and the Serial Presence Detect is a reliable and consistent way to document the features of these new modules so that system software can tune system performance," said Mian Quddus, Chairman of JEDEC's JC-45 Committee for Dynamic Random Access Memory (DRAM) Modules. He added, "This release of the DDR3 SPD standard adds support for memory modules with up to 8 ranks of DDR3 SDRAMs, enabling 64GB per slot using mainstream 4Gb memory chips."