Intel CEO Pat Gelsinger made the first official reference to the company's future-generation client processor, codenamed "Meteor Lake." Slated for market release in 2023, the processor's compute tile will be taped out in Q2-2021. Launching alongside the "Granite Rapids" enterprise processor, "Meteor Lake" will be a multi-chip module leveraging Intel's Foveros chip packaging technology.

Different components of the processor will be fabricated on different kinds of silicon fabrication nodes, and interconnected on the package using EMIB inter-die connections, or even silicon interposers. The compute tile is likely the tile containing the processor's CPU cores, and Intel confirmed a 7 nm-class foundry node for it. "Meteor Lake" will be a hybrid processor, much like the upcoming "Alder Lake," meaning that it will have two kinds of CPU cores, larger "high performance" cores that remain dormant when the machine is idling or dealing with lightweight workloads; and smaller "high efficiency" cores based on a low-power microarchitecture.

Intel Corporation today reported second-quarter 2020 financial results. "It was an excellent quarter, well above our expectations on the continued strong demand for computing performance to support cloud-delivered services, a work- and learn-at-home environment, and the build-out of 5G networks," said Bob Swan, Intel CEO. "In our increasingly digital world, Intel technology is essential to nearly every industry on this planet. We have an incredible opportunity to enrich lives and grow this company with a continued focus on innovation and execution."

Intel achieved record second-quarter revenue with 34 percent data-centric revenue growth and 7 percent PC-centric revenue growth YoY. These results were driven by strong sales of cloud, notebook, memory and 5G products in an environment where digital services and computing performance are essential to how we live, work and stay connected.

A performance review of the Intel Core i5-L16G7 "Lakefield" Hybrid processor (powering a Samsung Galaxy S notebook) was recently published by Golem.de, which provides an in-depth look at Intel's ambitious new processor design that sets in motion the two new philosophies Intel will build its future processors on - packaging modularity provided by innovative new chip packaging technologies such as Foveros; and Hybrid processing, where there are two sets of CPU cores with vastly different microarchitectures and significantly different performance/Watt curves that let the processor respond to different kinds of workloads while keeping power-draw low. This concept was commercially proliferated first by Arm, with its big.LITTLE topology that took to the market around 2013. The "Lakefield" i5-L16G7 combines a high-performance "Sunny Cove" CPU core with four smaller "Tremont" cores, and Gen11 iGPU.

The Golem.de report reveals that Windows 10 thread scheduler is aware of the hybrid multi-core topology of "Lakefield," and that it is able to classify workloads at a very advanced level so the right kind of core is in use at any given time. The "Sunny Cove" core is called upon when interactive vast serial processing loads are in demand. This could even be something like launching applications, new tabs in a multi-process web-browser, or less-parallelized media encoding. The four "Tremont" cores keep the machine "cruising," handling much of the operational workload of an application, and is also better tuned to cope with highly parallelized workloads. This is similar to a hybrid automobile, where the combustion engine provides tractive effort from 0 kph, while the electric motor sustains a cruising speed.

Performance benchmarks have started leaking for Intel-s upcoming Lakefield CPUs - low-power SoCs designed with Intel's latest technology. The Lakefield family of CPUs will make use of an Arm-similar big.LITTLE design, where this particular CPU, the Core i5-L16G7, will ship with four low-power "Tremond" cores and one large, high-performance "Sunny Cove" core for peak workloads. Built using Intel's Foveros stacking technology, these are the first chips to be built on Intel's modular platform, which should allow for pairing of I/O dies, chiplet-like CPU arrangements and memory in a 3D package. Physical distance reductions impact latency and power consumption, which should allow for an interesting design result.

Notebookcheck has tested an Intel Lakefield Core i5-L16G7 CPU that's being deployed on upcoming Samsung's Galaxy Book S, and the results are sort of a mixed bag. For one, Intel's Lakefield seems to be around 67% slower than the company's previous ultra-low-power architecture, Amber Lake. Something of this might have been caused by the fact that the Lakefield CPU didn't boost towards its advertised 3.0 GHz; it only managed to reach 2.4 GHz, which obviously hampered performance. Perhaps pre-release silicon is the culprit, or perhaps it's the galaxy Book S that's been configured with more restrictive thermal and power characteristics than the chip was actually designed to run at. The chip did manage to run the FireStrike test beating the Amber Lake-based Acer Swift 7 by 23%, though, so not all is looking bleak.

Apple on Monday formalized the beginning of its departure from Intel x86 machine architecture for its Mac computers. Apple makes up to 4 percent of Intel's annual CPU sales, according to a MarketWatch report. Apple is now scaling up its own A-series SoCs that use Arm CPU cores, up to performance levels relevant to Macs, and has implemented support for not just new and upcoming software ported to the new Arm machine architecture, but also software over form the iOS and iPadOS ecosystems on Mac, starting with its MacOS "Big Sur" operating system. We reached out to Intel for some of its first comments on the development.

In a comment to TechPowerUp, an Intel spokesperson said "Apple is a customer across several areas of our business, and we will continue to support them. Intel remains focused on delivering the most advanced PC experiences and a wide range of technology choices that redefine computing. We believe Intel-powered PCs—like those based on our forthcoming Tiger Lake mobile platform—provide global customers the best experience in the areas they value most, as well as the most open platform for developers, both today and into the future."

Today, Intel launched Intel Core processors with Intel Hybrid Technology, code-named "Lakefield." Leveraging Intel's Foveros 3D packaging technology and featuring a hybrid CPU architecture for power and performance scalability, Lakefield processors are the smallest to deliver Intel Core performance and full Windows compatibility across productivity and content creation experiences for ultra-light and innovative form factors.

"Intel Core processors with Intel Hybrid Technology are the touchstone of Intel's vision for advancing the PC industry by taking an experience-based approach to designing silicon with a unique combination of architectures and IPs. Combined with Intel's deepened co-engineering with our partners, these processors unlock the potential for innovative device categories of the future," said Chris Walker, Intel corporate vice president and general manager of Mobile Client Platforms.

Samsung Electronics today announced the availability of Galaxy Book S with Intel processor, the latest addition to its leading computing device family. To ensure consumers have access to a wide range of computing devices to best fit their lifestyle, Samsung introduces the Galaxy Book S powered by the new dynamic Intel Core processor with Intel Hybrid Technology. Galaxy Book S joins other previously announced premium mobile laptops, designed to offer a seamless and connected experience across devices. Galaxy Book S is built for the next generation of users who are looking for a computing device that provides outstanding productivity, wide-ranging connectivity, enhanced mobility and expansive continuity across devices and operating systems to help them get more done in less time.

"The way we work has shifted and it's important we have computing devices that can adapt to this new working style. Users utilize multiple devices throughout their day to accomplish tasks, and demand that those devices provide them with enough flexibility to remain on the move and available," said Woncheol Chai, SVP and Head of Product Planning Team, Mobile Communications Business, Samsung Electronics. "With our new computing devices like the Galaxy Book S, we are providing users with an exciting opportunity to be productive, efficient and connected."

One of the first Intel "Lakefield" heterogenous processor-powered devices, a Samsung Galaxy Book S model, is listed by Samsung on its Canadian online store. The Galaxy Book series typically consists of Arm-powered clamshell/convertible notebooks that use Windows 10 (Arm version). The device in question is a Galaxy Book S 13.3-inch notebook bearing model number NP767XCM-K01CA, and comes in two color trims - "Mercury Gray" and "Earthy Gold."

Under the hood is an Intel Core i5-L16G7 "Lakefield" heterogenous processor that has four "Tremont" low-power cores, and a "Sunny Cove" high-performance cores, in an arrangement rivaling Arm big.LITTLE, the first of many such chips from the company, as it taps into new technologies such as heterogenous cores and advanced Foveros chip packaging to design its future processors. The notebook offers Full HD resolution, 8 GB of RAM, 256 GB or 512 GB of solid-state NVMe storage, 802.11ax 2x2 WLAN, and a 42 Wh battery, possibly with double-digit hour battery life. All of this goes into a 6.2 mm (folded) device weighing under a kilogram.

Intel's silicon fabrication technological edge over TSMC and Samsung may have buckled, but the company appears to have made big advances in chip packaging. We've known for some time about EMIB (embedded multi-die interconnect bridge), Intel's cost-effective alternative to using full-fledged interposers; and Foveros heterogenous multi-die packaging; but the company has apparently invented more forms of 3-D chip stacking, as detailed by a WikiChip Fuse report. By leveraging ODI (omni-directional interconnect), an evolutionary next-step to EMIB and Foveros, Intel is able to stack multiple chips above the fiberglass substrate, above each other; and inside indentations and cavities of the substrate.

ODI consists of EMIB-like silicon dies that enable high-density wiring between two dies (think a GPU and its memory stack, or an SoC and core-logic); and copper poles that serve as extensions of the bumps of silicon dies getting to the substrate. There are two types of ODI. Type-1 refers to an interconnect running between two top dies, with the ODI die sitting between them and the substrate at the point of the inter-die connection region; while copper poles compensate for the Z-height difference. In scenarios without copper poles, chip designers can opt for substrates with cavities (regions with fewer layers), where the ODI die can be slotted in. In type-2 ODI, the interconnect die sits completely under a top die, providing high-density wiring either between two regions of the same die, or between two dies. The two types can be mixed and matched to achieve extremely complex MCMs.

The 11th generation Intel Core "Tiger Lake" mobile processor and pioneering "Lakefield" heterogenous x86 processor could debut around September or October, 2020, according to a leaked Lenovo internal slide posted by NotebookCheck. It also points to Intel denoting future processors' lithography with Foveros 3D Packaging as simply "3D," and not get into a nanometer number-game with AMD (which is now in 7 nm and on course to 5 nm in 2022). This makes sense as Foveros allows the combination of dies built on different silicon fabrication nodes.

"Tiger Lake" is still denoted as a 10 nm as it's a planar chip. Intel is developing it on a refined 10 nm+ silicon fabrication process, which apparently enables Intel to increase clock speeds without breaking the target power envelope. "Tiger Lake" sees the commercial debut of Intel's ambitious Xe graphics architecture as an iGPU solution. "Lakefield," on the other hand, is a 5-core processor combining four "Tremont" low power x86-64 cores with a "Sunny Cove" high-powered core, in a setup rivaling Arm big.LITTLE, enabling the next generation of mobile computing form-factors, which Intel and its partners are still figuring out under Project Athena.

Intel is preparing lots of interesting designs for the future and it is slowly shaping their vision for the next generation of computing devices. Following the big.LITTLE design principle of Arm, Intel decided to try and build its version using x86-64 cores instead of Arm ones, called Lakefield. And we already have some information about the new Alder Lake CPUs based on Lakefield design that are set to be released in the future. Thanks to a report from Chrome Unboxed, who found the patches submitted to Chromium open-source browser, used as a base for many browsers like Google Chrome and new Microsoft Edge, there is a piece of potential information that suggests Alder Lake CPUs could arrive very soon.

Rumored to feature up to 16 cores, Alder Lake CPUs could present an x86 iteration of the big.LITTLE design, where one pairs eight "big" and eight "small" cores that are activated according to increased or decreased performance requirements, thus bringing the best of both worlds - power efficiency and performance. This design would be present on Intel's 3D packaging technology called Foveros. The Alder Lake CPU support patch was added on April 27th to the Chrome OS repository, which would indicate that Intel will be pushing these CPUs out relatively quickly. The commit message titled "add support for ADL gpiochip" contained the following: "On Alderlake platform, the pinctrl (gpiochip) driver label is "INTC105x:00", hence declare it properly." The Chrome Unboxed speculates that Alder Lake could come out in mid or late 2021, depending on how fast Intel could supply OEMs with enough volume.

AMD Financial Analyst Day presents an opportunity for AMD to talk straight with the finance industry about the company's current financial health, and a taste of what's to come. Guidance and product teasers made during this time are usually very accurate due to the nature of the audience. In this live blog, we will post information from the Financial Analyst Day 2020 as it unfolds.20:59 UTC: The event has started as of 1 PM PST. CEO Dr Lisa Su takes stage.

The fingernail-size Intel chip with Foveros technology is a first-of-its kind. With Foveros, processors are built in a totally new way: not with the various IPs spread out flat in two dimensions, but with them stacked in three dimensions. Think of a chip designed as a layer cake (a 1-millimeter-thick layer cake) versus a chip with a more-traditional pancake-like design. Intel's Foveros advanced packaging technology allows Intel to "mix and match" technology IP blocks with various memory and I/O elements - all in a small physical package for significantly reduced board size. The first product designed this way is "Lakefield," the Intel Core processor with Intel hybrid technology.

Industry analyst firm The Linley Group recently named Intel's Foveros 3D-stacking technology as "Best Technology" in its 2019 Analysts' Choice Awards. "Our awards program not only recognizes excellence in chip design and innovation, but also acknowledges the products that our analysts believe will have an impact on future designs," said Linley Gwennap, of The Linley Group.

A reportedly leaked Intel slide via DigitalTrends has given us a load of information on Intel's upcoming take on the high performance graphics accelerators market - whether in its server or consumer iterations. Intel's Xe has already been cause for much discussion in a market that has only really seen two real competitors for ages now - the coming of a third player with muscles and brawl such as Intel against the already-established players NVIDIA and AMD would surely spark competition in the segment - and competition is the lifeblood of advancement, as we've recently seen with AMD's Ryzen CPU line.

The leaked slide reveals that Intel will be looking to employ a Multi-Chip-Module (MCM) approach to its high performance "Arctic Sound" graphics architecture. The GPUs will be available in up to 4-tile configuration (the name Intel is giving each module), which will then be joined via Foveros 3D stacking (first employed in Intel Lakefield. This leaked slide shows Intel's approach starting with a 1-tile GPU (with only 96 of its 128 total EUs active) for the entry level market (at 75 W TDP) a-la DG1 SDV (Software Development Vehicle).

Intel Core i5-L16G7 is the first commercial SKU that implements Intel's "Lakefield" heterogenous x86 processor architecture. This 5-core chip features one high-performance "Sunny Cove" CPU core, and four smaller "Tremont" low-power cores, with an intelligent scheduler balancing workloads between the two core types. This is essentially similar to ARM big.LITTLE. The idea being that the device idles most of the time, when lower-powered CPU cores can hold the fort; performance cores kick in only when really needed, until which time they remain power-gated. Thai PC enthusiast TUM_APISAK discovered the first public appearance of the i5-L16G7 in an unreleased Samsung device that has the Userbenchmark device ID string "SAMSUNG_NP_767XCL."

Clock speeds of the processor are listed as "1.40 GHz base, with 1.75 GHz turbo," but it's possible that the two core types have different clock-speed bands, just like the cores on big.LITTLE SoCs. Other key components of "Lakefield" include an iGPU based on the Gen11 graphics architecture, and an LPDDR4X memory controller. "Lakefield" implements Foveros packaging, in which high-density component dies based on newer silicon fabrication nodes are integrated with silicon interposers based on older fabrication processes, which facilitate microscopic high-density wiring between the dies. In case of "Lakefield," the Foveros package features a 10 nm "compute field" die sitting atop a 22 nm "base field" interposer.

At Supercomputing 2019, Intel unveiled its vision for extending its leadership in the convergence of high-performance computing (HPC) and artificial intelligence (AI) with new additions to its data-centric silicon portfolio and an ambitious new software initiative that represents a paradigm shift from today's single-architecture, single-vendor programming models.

Addressing the increasing use of heterogeneous architectures in high-performance computing, Intel expanded on its existing technology portfolio to move, store and process data more effectively by announcing a new category of discrete general-purpose GPUs optimized for AI and HPC convergence. Intel also launched the oneAPI industry initiative to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The launch of oneAPI represents millions of Intel engineering hours in software development and marks a game-changing evolution from today's limiting, proprietary programming approaches to an open standards-based model for cross-architecture developer engagement and innovation.

What's New: This week at SEMICON West in San Francisco, Intel engineering leaders provided an update on Intel's advanced packaging capabilities and unveiled new building blocks, including innovative uses of EMIB and Foveros together and a new Omni-Directional Interconnect (ODI) technology. When combined with Intel's world-class process technologies, new packaging capabilities will unlock customer innovations and deliver the computing systems of tomorrow.

"Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip. A heterogeneous approach gives our chip architects unprecedented flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors. Intel's vertically integrated structure provides an advantage in the era of heterogeneous integration, giving us an unmatched ability to co-optimize architecture, process and packaging to deliver leadership products." -Babak Sabi, Intel corporate vice president, Assembly and Test Technology Development.