Responding to investor questions in TSMC's first quarter earnings call for 2022, CEO C. C. Wei reiterated that the company's upcoming manufacturing processes are generally moving smoothly throughout development. Even as TSMC announced historic revenues on the back of increased pricing throughout the semiconductor industry, the company is showing no signs of slowing down on its development. When further asked regarding the company's ability to navigate the world's troubled, inflation-ridden waters, Wei added that TSMC's strategic positioning as the leading semiconductor foundry makes it resilient to market and demand fluctuations.

TSMC's roadmap has seen multiple accelerations of late, which have placed 3 nm tape-out to occur before the end of the year. Perhaps more significantly, the company's next-generation 2 nm manufacturing process, which will make use of GAA (Gate All Around) transistor designs for greater design efficiency and density, are still on track for a 2025 volume production following an expected 2024 tape-out.

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company's Gate-All-Around (GAA) transistor structure at its 5th annual Samsung Foundry Forum (SFF) 2021. With a theme of "Adding One More Dimension," the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year's event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations, and foundry services.

"We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time."

NVIDIA (NASDAQ: NVDA) today reported record revenue for the second quarter ended August 1, 2021, of $6.51 billion, up 68 percent from a year earlier and up 15 percent from the previous quarter, with record revenue from the company's Gaming, Data Center and Professional Visualization platforms. GAAP earnings per diluted share for the quarter were $0.94, up 276 percent from a year ago and up 24 percent from the previous quarter. Non-GAAP earnings per diluted share were $1.04, up 89 percent from a year ago and up 14 percent from the previous quarter.

"NVIDIA's pioneering work in accelerated computing continues to advance graphics, scientific computing and AI," said Jensen Huang, founder and CEO of NVIDIA. "Enabled by the NVIDIA platform, developers are creating the most impactful technologies of our time - from natural language understanding and recommender systems, to autonomous vehicles and logistic centers, to digital biology and climate science, to metaverse worlds that obey the laws of physics.

During the IEEE International Solid-State Circuits Conference (ISSCC), Samsung Foundry has presented a new step towards smaller and more efficient nodes. The new chip that was presented is a 256 Gb memory chip, based on SRAM technology. However, all of that doesn't sound interesting, until we mention the technology that is behind it. Samsung has for the first time manufactured a chip using the company's gate-all-around field-effect transistor (GAAFET) technology on the 3 nm semiconductor node. Formally, there are two types of GAAFET technology: the regular GAAFET that uses nanowires as fins of the transistor, and MBCFET (multi-bridge channel FET) that uses thicker fins that come in a form of a nanosheet.

Samsung has demonstrated the first SRAM chip that uses MBCFET technology today. The chip in question is a 256 Gb chip with an area of 56 mm². The achievement Samsung is proud of is that the chip uses 230 mV less power for writes, compared to the standard approach, as the MBCFET transistors allow the company to have many different power-saving techniques. The new 3 nm MBCFET process is expected to get into high-volume production sometime in 2022, however, we are yet to see demos of logic chips besides SRAM like we see today. Nonetheless, even the demonstration of SRAM is big progress, and we are eager to see what the company manages to build with the new technology.

Samsung has been one of the world's biggest foundries and one of three big players still left in the leading-edge semiconductor process development and manufacturing. However, the Korean giant is always seeking ways to improve its offerings, especially for Western customers. Today, it is reported that Samsung has reportedly talked with regulators in Texas, New York, and Arizona about building a $17 billion silicon manufacturing facility in the United States. The supposed factory is going to be located near Austin, Texas, and is supposed to offer around 1800 jobs. If the deal is approved and Samsung manages to complete the project on time, the factory is supposed to start mass production in Q4 of 2023.

What process is Samsung going to manufacture in the new fab? Well, current speculations are pointing out to the 3 nm node, with Samsung's special GAAFET (Gate All Around FET) technology tied to the new node. The fab is also expected to make use of extreme ultraviolet (EUV) lithography for manufacturing. Samsung already has a facility in the US called S2, however, that will not be upgraded as it is still serving a lot of clients. Instead, the company will build new facilities to accommodate the demand for newer nodes. It is important to note that Samsung will not do any R&D work in the new fab, and the company will only manufacture the silicon there.

The Taiwan Economic Daily claims that TSMC has achieved a major internal breakthrough for the eventual rollout of 2 nm fabrication process technology. According to the publication, this breakthrough has turned TSMC even more optimistic towards a 2023 rollout of 2 nm risk production - which is all the more impressive considering reports that TSMC will be leaving the FinFet realm for a new multi-bridge channel field effect transistor (MBCFET) architecture - itself based on the Gate-All-Around (GAA) technology. This breakthrough comes one year after TSMC put together an internal team whose aim was to pave the way for 2 nm deployment.

MBCFET expands on the GAAFET architecture by taking the Nanowire field-effect transistor and expanding it so that it becomes a Nanosheet. The main idea is to make the field-effect transistor three-dimensional. This new complementary metal oxide semiconductor transistor can improve circuit control and reduce leakage current. This design philosophy is not exclusive to TSMC - Samsung has plans to deploy a variant of this design on their 3 nm process technology. And as has been the norm, further reductions in chip fabrication scale come at hefty costs - while the development cost for 5 nm has already achieved $476M in cost, Samsung reports that their 3 nm GAA technology will cost in excess of $500M - and 2 nm, naturally, will come in even costlier than that.