We know AMD has been doing a great job keeping the lid on their Navi architecture with information being scarce at the moment. Aside from knowing that Navi is being fabricated on the 7 nm process, it is possible that the microarchitecture will quite possibly support next-generation memory like GDDR6 or HBM3. In a Navi discussion on the Beyond3D forums, a user found an entry in a Linux driver dated back to July that apparently mentions AMD's upcoming architecture - not by its real name, of course. The code is to add support for importing new asic definitions from a text file as opposed to adding support in code. Tom St Denis, a software engineer at AMD, listed the output that would be generated by using this functionality. However, the entry that caught our attention reads: new_chip.gfx10.mmSUPER_SECRET.enable [0: 0]. If our memory serves us right, the codename for Vega was GFX9. So by logic, Navi should carry the GFX10 codename. Obviously, the SUPER_SECRET part further backs up our theory or maybe AMD's just trolling us. The red team has been hiring personnel for their GFX10 projects, so we can assume they're working diligently to release Navi some time next year.

Rambus, a company that has veered around the line of being an innovative company and a patent troll, has shed some more light on what can be expected from HBM3 memory (when it's finally available). In an investor meeting, representatives from the company shared details regarding HBM3's improvements over HBM2. Details are still scarce, but at least we know Rambus' expectations for the technology: double the memory bandwidth per stack when compared to HBM2 (4000 MB/s), and a more complex design, which leaves behind the 2.5D design due to increased height of the HBM3 memory stacks. An interesting thing to note is that Rambus is counting on HBM3 to be produced on 7 nm technologies. Considering the overall semiconductor manufacturing calendar for the 7 nm process, this should place HBM3 production in 2019, at the earliest.

HBM3 is also expected to bring much lower power consumption compared to HBM2, besides increasing memory density and bandwidth. However, the "complex design architectures" in the Rambus slides should give readers pause. HBM2 production has had some apparent troubles in reaching demand levels, with suspected lower yields than expected being the most likely culprit. Knowing the trouble AMD has had in successful packaging of HBM2 memory with the silicon interposer and its own GPUs, an even more complex implementation of HBM memory in HBM3 could likely signal some more troubles in that area - maybe not just for AMD, but for any other takers of the technology. Here's hoping AMD's woes were due only to one-off snags on their packaging partners' side, and doesn't spell trouble for HBM's implementation itself.

Even as its fellow-Korean DRAM maker SK Hynix is pushing for HBM3 to bring 2 TB/s memory bandwidths to graphics cards, Samsung is betting on relatively inexpensive standards that succeed existing ones. The company hopes to have GDDR6, the memory standard that succeeds GDDR5X, to arrive by 2018.

GDDR6 will serve up bandwidths of up to 16 Gbps, up from the 10 Gbps currently offered by GDDR5X. This should enable memory bandwidths of 512 GB/s over a 256-bit wide memory interface, and 768 GB/s over 384-bit. The biggest innovation with GDDR6 that sets it apart from GDDR5X is LP4X, a method with which the memory controller can more responsively keep voltages proportionate to clocks, and reduce power-draw by up to 20% over the previous standard.

One of the first drafts of the HBM3 specification reveals that the standard could enable graphics cards with up to 64 GB of video memory. The HBM2 memory, which is yet to make its consumer graphics debut, caps out at 32 GB, and the first-generation HBM, which released with the AMD Radeon Fury series, at just 4 GB.

What's more, HBM3 doubles bandwidth over HBM2, pushing up to 512 GB/s per stack. A 4096-bit HBM3 equipped GPU could have up to 2 TB/s (yes, terabytes per second) of memory bandwidth at its disposal. SK Hynix, one of the key proponents of the HBM standard, even claims that HBM3 will be both more energy-efficient and cost-effective than existing memory standards, for the performance on offer. Some of the first HBM3 implementations could come from the HPC industry, with consumer implementations including game consoles, graphics cards, TVs, etc., following later.