GIGABYTE's AERO line of motherboards and notebooks target creators who like to game. The company is ready with a premium motherboard based on the Intel Z690 chipset, the Z690 AERO D. This has to be the prettiest looking motherboard we've come across in a long time, and it appears to have the chops to match this beauty. The Socket LGA1700 motherboard uses large ridged-aluminium heatsinks over the chipset, M.2 NVMe slots, and a portion of the rear I/O shroud. Aluminium fin-stack heatsinks fed by heat-pipes, cool the CPU VRM. You get two PCI-Express 5.0 x16 slots (x8/x8 with both populated). As an AERO series product, the board is expected to be loaded with connectivity relevant to content creators, although the box is missing a Thunderbolt logo. We expect at least 20 Gbps USB 3.2x2 ports, and 10 GbE networking, Wi-Fi 6E.

Presenting at the China Flash-Market Summit, KIOXIA unveiled its plans to leverage PCI-Express 5.0 to double SSD performance over the current generation. In typical 4-lane U.2 and M.2 connections, PCI-Express Gen 5 enables an interface bandwidth of 16 GB/s per direction (comparable to PCI-Express 3.0 x16). This means that accounting for interface overheads, typical PCIe Gen 5 SSDs will dance around the 11-15 GB/s (sequential) range. KIOXIA unveiled the CD7, a prototype enterprise SSD in the 2.5-inch EDSFF E3S form-factor with U.2 PCI-Express 5.0 x4 interface. This drive, the company claims, offers up to 14 GB/s sequential transfers, more than double the performance of the current CM6 series drives that leverage PCI-Express Gen 4.

KIOXIA said that its first PCI-Express Gen 5 SSDs will begin shipping in Q4-2021, although it didn't mention if this was mass-market, or to select customers. The first enterprise platforms to leverage Gen 5 won't arrive before mid-2022, with Intel's Xeon "Sapphire Rapids" processors that feature PCI-Express Gen 5 support. KIOXIA sounded optimistic about the future growth in performance of SSDs. "Today, Moore's Law is technically dead in both the CPU and DRAM, but it still works at the PCIe clock rate," the company said, adding ""2015 [was] be the third generation of PCIe, 2019 is the fourth generation, and 2022 will be the fifth generation. Even if people spend a lot of money, they can't double CPU nodes to improve system performance, but buying Gen 5 SSD instead of Gen 4 SSD can greatly improve system performance."

Xilinx, Inc., the leader in adaptive computing, today introduced the Versal HBM adaptive compute acceleration platform (ACAP), the newest series in the Versal portfolio. The Versal HBM series enables the convergence of fast memory, secure connectivity, and adaptable compute in a single platform. Versal HBM ACAPs integrate the most advanced HBM2E DRAM, providing 820 GB/s of throughput and 32 GB of capacity for 8X more memory bandwidth and 63% lower power than DDR5 implementations. The Versal HBM series is architected to keep up with the higher memory needs of the most compute intensive, memory bound applications for data center, wired networking, test and measurement, and aerospace and defense.

"Many real-time, high-performance applications are critically bottlenecked by memory bandwidth and operate at the edge of their power and thermal limits," said Sumit Shah, senior director, Product Management and Marketing at Xilinx. "The Versal HBM series eliminates those bottlenecks to provide our customers with a solution that delivers significantly higher performance and reduced system power, latency, form factor, and total cost of ownership for data center and network operators."

Intel's 12th Gen Core "Alder Lake-S" desktop processors in the LGA1700 package could see the desktop debut of Intel's Hybrid Technology that it introduced with the mobile segment "Lakefield" processor. Analogous to Arm big.LITTLE, Intel Hybrid Technology is a multi-core processor topology that sees the combination of high-performance CPU cores with smaller high-efficiency cores that keep the PC ticking through the vast majority of the time/tasks when the high-performance cores aren't needed and hence power-gated. The high-performance cores are woken up only as needed. "Lakefield" combines one "Sunny Cove" high-performance core with four "Tremont" low-power cores. "Alder Lake-S" will take this concept further.

According to Intel slides leaked to the web by HXL (aka @9550pro), the 10 nm-class "Alder Lake-S" silicon will physically feature 8 "Golden Cove" high-performance cores, and 8 "Gracemont" low-power cores, along with a Gen12 iGPU that comes in three tiers - GT0 (iGPU disabled), GT1 (some execution units disabled), and GT2 (all execution units enabled). In its top trim with 125 W TDP, "Alder Lake-S" will be a "16-core" processor with 8 each of "Golden Cove" and "Gracemont" cores enabled. There will be 80 W TDP models with the same 8+8 core configuration, which are probably "locked" parts. Lastly, there the lower wrungs of the product stack will completely lack "small" cores, and be 6+0, with only high-performance cores. A recurring theme with all parts is the GT1 trim of the Gen12 iGPU.

Intel has finalized design of its next-generation Xeon Scalable enterprise CPU socket for its "Sapphire Rapids" processors. Called LGA4677, the socket succeeds LGA3647, and is bound for a 2021 market release. Intel will have transitioned to its advanced 7 nm EUV silicon fabrication node on the CPU front, and has adopted an "enterprise-first" strategy for the node. LGA4677 will be designed to handle the extremely high bandwidth of PCI-Express Gen 5, which doubles bandwidth over PCIe gen 4.0, and adds several enterprise-specific features Intel is rolling out in advance as part of its CXL interconnect. These details, along with a prototype LGA4189 socket, was revealed at an exhibit by TE Connectivity, a company that manufactures the socket. The additional pin-count could enable Intel to not just deploy PCI-Express Gen 5, but also expand I/O in other directions, such as more memory channels, dedicated Persistent Memory I/O, etc.

PCI-SIG today announced the release of PCI Express (PCIe ) 5.0 specification, reaching 32 GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations. "New data-intensive applications are driving demand for unprecedented levels of performance," said Al Yanes, PCI-SIG Chairman and President. "Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the de facto standard for high performance I/O for the foreseeable future."

"For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software," noted Nathan Brookwood, research fellow at Insight 64. "Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow2. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly."

Intel has been working on CXL, short for Compute Express Link gen 1, for over four years new. This new interconnect protocol was donated to a new consortium of tech companies for release as a the CXL 1.0 standard. Its protocol layer will pave the way for PCI-Express gen 5.0 to sustain its bandwidth growth target of being twice as fast as PCIe gen 4.0. CXL 1.0 is out to compete with other established PCIe-alternative slot standards such as NVLink from NVIDIA, and InfinityFabric from AMD. It has one killer advantage, though: the CXL 1.0 is pin-compatible and backwards-compatible with PCI-Express, and uses PCIe physical-layer and electrical interface.

This reduces hardware upgrade costs for data-centers. CXL maintains memory coherency between the CPU's memory-space and memory on installed devices. The CXL Consortium, or SIG, includes data-center and cloud-computing giants, including Alibaba, Cisco, DellEMC, Facebook, Google, HPE, Huawei, Microsoft, and of course Intel. CXL will be used bot as a socketed/slotted interface for add-on cards and GPU boards, and as an embedded interface. We estimate bandwidth of CXL to be 32 Gbps per lane, or four times that of PCIe gen 3.0, keeping in line with PCIe gen 5.0 bandwidth growth estimates.

PCI-SIG Developers Conference 2017 - PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) industry-standard input/output (I/O) technology, today announced 32GT/s as the next progression in speed for the PCIe 5.0 architecture, targeting high-performance applications such as artificial intelligence, machine learning, gaming, visual computing, storage and networking. Slated for completion in 2019, the specification development is well underway with Revision 0.3 already available to PCI-SIG member companies.

"In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O," said Al Yanes, PCI-SIG Chairman and President. "PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs."

The preceding PCIe 4.0 specification is designed with key functional enhancements that future-proof the PCIe architecture design, thereby accelerating future specification development. This undertaking, along with improved silicon design processes, serves as the foundation for the PCIe 5.0 specification.