The National Renewable Energy Laboratory (NREL) has selected Hewlett Packard Enterprise (HPE) to build its third-generation, high performance computing (HPC) system, called Kestrel. Named for a falcon with keen eyesight and intelligence, Kestrel's moniker is apropos for its mission—to rapidly advance the U.S. Department of Energy's (DOE's) energy research and development (R&D) efforts to deliver transformative energy solutions to the entire United States.

Installation of the new system will begin in the fall of 2022 in NREL's Energy Systems Integration Facility (ESIF) data center. Kestrel will complement the laboratory's current supercomputer, Eagle, during the transition. When completed—in early 2023—Kestrel will accelerate energy efficiency and renewable energy research at a pace and scale more than five times greater than Eagle, with approximately 44 petaflops of computing power.

During the Supercomputing (SC) 21 event, Intel has disclosed additional information regarding the company's upcoming Xeon server processor lineup, codenamed Sapphire Rapids. One of the central areas of improvement for the new processor generation is the core architecture based on Golden Cove, the same core found in Alder Lake processors for consumers. However, the only difference between the Golden Cove variant found in Alder Lake and Sapphire Rapids is the amount of L2 (level two) cache. With Alder Lake, Intel equipped each core with 1.25 MB of its L2 cache. However, with Sapphire Rapids, each core receives a 2 MB bank.

One of the most exciting things about the processors, confirmed by Intel today, is the inclusion of High-Bandwidth Memory (HBM). These processors operate with eight memory channels carrying DDR5 memory and offer PCIe Gen5 IO expansion. Intel has confirmed that Sapphire Rapids Xeons will feature up to 64 GB of HBM2E memory, including a few operating modes. The first is a simple HBM caching mode, where the HBM memory acts as a buffer for the installed DDR5. This method is transparent to software and allows easy usage. The second method is Flat Mode, which means that both DDR5 and HBM are used as contiguous address spaces. And finally, there exists an HBM-only mode that utilizes the HBM2E modules as the only system memory, and applications fit inside it. This has numerous benefits, primarily drawn from HBM's performance and reduced latency.

Intel's Aurora supercomputer is a $500 million contract with the US Department of Energy to deliver an exascale supercomputer for Argonne National Laboratory. The project aims to build a machine capable of cranking over one ExaFLOP of computing at sustained workloads. The supercomputer aims to reach two ExaFLOPs of computing power once the installation system is completed and powered. The contract bound Intel to create accelerators that are powerful enough to achieve this magical number. However, they left Intel with room to do a little bit extra. With Ponte Vecchio GPU behind the project, it seems like the GPU is performing better than expected.

According to Intel's CEO, Pat Gelsinger, the system will reach over 2 ExaFLOPs at peak and a bit below in sustained workloads. As per preliminary calculations done by The Next Platform, the system's estimations point towards 2.43 ExaFLOPs peak and around 1.7 ExaFLOPs in sustained workloads at Double-precision floating-point format math, aka FP64. The system will utilize Intel Xeon Sapphire Rapids processors with HBM memory and the powerful Ponte Vecchio GPU with 47 tiles and over 100 billion transistors.

Intel Corporation today reported third-quarter 2021 financial results. "Q3 shone an even greater spotlight on the global demand for semiconductors, where Intel has the unique breadth and scale to lead. Our focus on execution continued as we started delivering on our IDM 2.0 commitments. We broke ground on new fabs, shared our accelerated path to regain process performance leadership, and unveiled our most dramatic architectural innovations in a decade. We also announced major customer wins across every part of our business," said Pat Gelsinger, Intel CEO. "We are still in the early stages of our journey, but I see the enormous opportunity ahead, and I couldn't be prouder of the progress we are making towards that opportunity."

In the third quarter, the company generated $9.9 billion in cash from operations and paid dividends of $1.4 billion. Intel CFO George Davis announced plans to retire from Intel in May 2022. He will continue to serve in his current role while Intel conducts a search for a new CFO and until his successor is appointed. Third-quarter revenue was led by strong recovery in the Enterprise portion of DCG and in IOTG, which saw higher demand amid recovery from the economic impacts of COVID-19. The Client Computing Group (CCG) was down due to lower notebook volumes due to industry-wide component shortages, and on lower adjacent revenue, partially offset by higher average selling prices (ASPs) and strength in desktop.

Contract prices of NAND Flash products are expected to undergo a marginal drop of 0-5% QoQ in 4Q21 as demand slows, according to TrendForce's latest investigations. Hence, the current cyclical upturn in NAND Flash prices will have lasted for only two consecutive quarters. Looking ahead, NAND Flash suppliers' capacity expansion plans will be affected by the outlook on future trends and the supply of other non-memory components. At the same time, attention will have to be paid to the demand projection. At the moment, NAND Flash suppliers appear likely to downsize their capacity expansion activities for 2022, resulting in a 31.8% YoY increase in NAND Flash bit supply next year. Annual bit demand, on the other hand, is projected to increase by 30.8% YoY. With demand being outpaced by supply and competition intensifying among suppliers for higher-layer products, the NAND Flash market will likely experience a cyclical downturn in prices in 2022.

DRAM contract prices are likely to exit a bullish period that lasted three quarters and be on the downswing in 4Q21 at a QoQ decline of 3-8%, according to TrendForce's latest investigations. This decline can be attributed to not only the declining procurement activities of DRAM buyers going forward, but also the drop in DRAM spot prices ahead of contract prices. While the buying and selling sides attempt to gain the advantage in future transactions, the DRAM market's movement in 2022 will primarily be determined by suppliers' capacity expansion strategies in conjunction with potential growths in demand. The capacity expansion plans of the three largest DRAM suppliers (Samsung, SK hynix, and Micron) for 2022 are expected to remain conservative, resulting in a 17.9% growth in total DRAM bit supply next year. On the demand side, inventory levels at the moment are relatively high. Hence, DRAM bit demand is expected to grow by 16.3% next year and lag behind bit supply growth. TrendForce therefore forecasts a shift in the DRAM market next year from shortage to surplus.

Launch of AMD's upcoming Ryzen Threadripper 5000 series high-end desktop (HEDT) and Threadripper WX workstation processors, is rumored to have been delayed to 2022, according to Greymon55, a reliable source with AMD leaks. Codenamed "Chagall," these processors are compatible with existing sTRX4 and sWRX8 motherboards, based on the AMD TRX40 and AMD WRX80 chipsets, respectively. What's new, is the "Zen 3" microarchitecture.

It remains to be seen if the delay is the result of a last-minute decision by AMD to go with the newer "Zen 3" CCD that comes with 3D Vertical Cache technology, over the conventional "Zen 3" CCD; or some other reason. A 2022 launch would mean that Threadripper 5000 series will be launching around the time when Intel has desktop platforms with DDR5 memory and PCI-Express Gen 5. Threadripper 5000 chips with quad-channel DDR4 memory (four 64-bit wide channels) will be seen offering only comparable memory bandwidth to "Alder Lake" systems with overclocked DDR5 memory (four 40-bit wide channels). AMD is likely to prioritize its next "big" socket for the enterprise segment with EPYC "Genoa," as the company could find itself embattled with Xeon "Sapphire Rapids" processors that come with next-gen I/O.

Presenting at the China Flash-Market Summit, KIOXIA unveiled its plans to leverage PCI-Express 5.0 to double SSD performance over the current generation. In typical 4-lane U.2 and M.2 connections, PCI-Express Gen 5 enables an interface bandwidth of 16 GB/s per direction (comparable to PCI-Express 3.0 x16). This means that accounting for interface overheads, typical PCIe Gen 5 SSDs will dance around the 11-15 GB/s (sequential) range. KIOXIA unveiled the CD7, a prototype enterprise SSD in the 2.5-inch EDSFF E3S form-factor with U.2 PCI-Express 5.0 x4 interface. This drive, the company claims, offers up to 14 GB/s sequential transfers, more than double the performance of the current CM6 series drives that leverage PCI-Express Gen 4.

KIOXIA said that its first PCI-Express Gen 5 SSDs will begin shipping in Q4-2021, although it didn't mention if this was mass-market, or to select customers. The first enterprise platforms to leverage Gen 5 won't arrive before mid-2022, with Intel's Xeon "Sapphire Rapids" processors that feature PCI-Express Gen 5 support. KIOXIA sounded optimistic about the future growth in performance of SSDs. "Today, Moore's Law is technically dead in both the CPU and DRAM, but it still works at the PCIe clock rate," the company said, adding ""2015 [was] be the third generation of PCIe, 2019 is the fourth generation, and 2022 will be the fifth generation. Even if people spend a lot of money, they can't double CPU nodes to improve system performance, but buying Gen 5 SSD instead of Gen 4 SSD can greatly improve system performance."

The U.S. Department of Energy's (DOE's) National Nuclear Security Administration (NNSA) selected next-generation Intel Xeon Scalable processors (code-named "Sapphire Rapids") to power the supercomputers used within NNSA's Life Extension Program for mission-critical efforts in stockpile stewardship. The NNSA's Lawrence Livermore National Laboratory awarded a subcontract to Dell Technologies to supply the Intel-powered computing systems that will be deployed at the NNSA's Tri-Labs (Lawrence Livermore National Laboratory, Los Alamos National Laboratory and Sandia National Laboratories).

Today's news supports the NNSA's Advanced Simulation and Computing (ASC) program operated at the NNSA's Tri-Labs. The Commodity Technology Systems contract (CTS-2) awarded today will enable these three national laboratories to build more powerful, energy-efficient computing systems that will focus on performing extensive modeling and simulation capabilities in support of NNSA's stockpile stewardship program.

The Chinese source who published the first images of the Intel LGA1700 socket and Z690 chipset has now revealed some new information regarding the upcoming Alder Lake, Sapphire Rapids-X, and Raptor Lake products. The rumor claims that Intel will launch the W790 Workstation HEDT chipset in Q3 2022 alongside the 13th Generation Sapphire Rapids-X desktop series. This would be the first new HEDT launch from Intel in over 3 years with the previous 10th Gen Cascade Lake processors launching back in April 2019.

The rumor also states that Intel will launch the 13th Generation Raptor Lake desktop processors at the same time as their Sapphire Rapids-X HEDT lineup. There is also a note about Intel releasing the entire 600-series motherboard lineup in 2021 which is contrary to previous rumors which stated that Intel would only make the Z690 chipset available this year. This would be followed by a complete launch of all 12 Generation Alder Lake desktop processors and not just the overclockable K-series. This is the first time we have heard these rumors so while they come from a semi-reliable leaker we would recommend taking them with a healthy dose of skepticism.

Intel has been working on a technology that will improve the lives of all users that have an Intel-based processor in their system. According to the recent round of patches for the Linux kernel, Intel's engineers have been working on a feature called Intel Seamless Update, which promises to bring updating of system firmware without a need to reboot. First of all, it is important to note that firmware upgrades have been stuck at requiring reboot in order to apply patches. This has caused many systems to be down and to slow down the infrastructure by a wide margin, as these updates can last up to several minutes, where the system is rebooting and can not be used.

Intel has presented an idea of creating a technology that will update system firmware, such as UEFI, in the run time. That means that the system will be able to apply firmware patches, without ever needing a reboot, minimizing downtime. This is especially valuable for customers with very high service level agreements (SLAs) around downtime, meaning that almost 100% uptime (not possible to be 100% generally speaking) is required for these systems. An example of this would be medical server infrastructure, which has to constantly be available for access. Using this technology, systems such as these could update their firmware and be online non-stop, without maybe ever needing to reboot. The said feature is supposed to arrive in time for the launch alongside Intel "Sapphire Rapids" Xeon processors.

Intel in its 2021 Architecture Day presentation put out fine technical details of its Xe HPC Ponte Vecchio accelerator, including some [very] preliminary performance claims for its current A0-silicon-based prototype. The prototype operates at 1.37 GHz, but achieves out at least 45 TFLOPs of FP32 throughput. We calculated the clock speed based on simple math. Intel obtained the 45 TFLOPs number on a machine running a single Ponte Vecchio OAM (single MCM with two stacks), and a Xeon "Sapphire Rapids" CPU. 45 TFLOPs sees the processor already beat the advertised 19.5 TFLOPs of the NVIDIA "Ampere" A100 Tensor Core 40 GB processor. AMD isn't faring any better, with its production Instinct MI100 processor only offering 23.1 TFLOPs FP32.

Intel's upcoming Xeon "Sapphire Rapids" processor features a memory interface topology that closely resembles that of first-generation AMD EPYC "Rome," thanks to the multi-chip module design of the processor. Back in 2017, Intel's competing "Skylake-SP" Xeon processors were based on monolithic dies. Despite being spread across multiple memory controller tiles, the 6-channel DDR4 memory interface was depicted by Intel as an advantage over EPYC "Rome." AMD's first "Zen" based enterprise processor was a multi-chip module of four 14 nm, 8-core "Zeppelin" dies, each with a 2-channel DDR4 memory interface that added up to the processor's 8-channel I/O. Much like "Sapphire Rapids," a CPU core from any of the four dies had access to memory and I/O controlled by any other die, as the four were networked over the Infinity Fabric interconnect in a configuration that essentially resembled "4P on a stick."

With "Sapphire Rapids," Intel is taking a largely similar approach—it has four compute tiles (dies) instead of a monolithic die, which Intel says helps with scalability in both directions; and each of the four compute tiles has a 2-channel DDR5 or 1024-bit HBM memory interface, which add up to the processor's 8-channel DDR5 total I/O. Intel says that CPU cores from each tile has equal access to memory, last-level cache, and I/O controlled by another die. Inter-tile communication is handled by EMIB physical media (55 micron bump-pitch wiring). UPI 2.0 makes up the inter-socket interconnect. Each of the four compute tiles has 24 UPI 2.0 links that operate at 16 GT/s. Intel didn't detail how memory is presented to the operating system, or the NUMA hierarchy, however much of Intel's engineering effort appears to be focused on making this disjointed memory I/O work as if "Sapphire Rapids" were a monolithic die. The company claims "consistent low-latency, high cross-sectional bandwidth across the SoC."

While the server industry transitions to the latest generation of processors based on the x86 platform, the Intel Ice Lake and AMD Milan CPUs entered mass production earlier this year and were shipped to certain customers, such as North American CSPs and telecommunication companies, at a low volume in 1Q21, according to TrendForce's latest investigations. These processors are expected to begin seeing widespread adoption in the server market in 3Q21. TrendForce believes that Ice Lake represents a step-up in computing performance from the previous generation due to its higher scalability and support for more memory channels. On the other hand, the new normal that emerged in the post-pandemic era is expected to drive clients in the server sector to partially migrate to the Ice Lake platform, whose share in the server market is expected to surpass 30% in 4Q21.

Intel Corporation today revealed one of the most detailed process and packaging technology roadmaps the company has ever provided, showcasing a series of foundational innovations that will power products through 2025 and beyond. In addition to announcing RibbonFET, its first new transistor architecture in more than a decade, and PowerVia, an industry-first new backside power delivery method, the company highlighted its planned swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV. Intel is positioned to receive the first High NA EUV production tool in the industry.

"Building on Intel's unquestioned leadership in advanced packaging, we are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025," Intel CEO Pat Gelsinger said during the global "Intel Accelerated" webcast. "We are leveraging our unparalleled pipeline of innovation to deliver technology advances from the transistor up to the system level. Until the periodic table is exhausted, we will be relentless in our pursuit of Moore's Law and our path to innovate with the magic of silicon."

We haven't seen any new prosumer HEDT processors since AMD launched their Ryzen Threadripper 3000 lineup in early 2020. Intel has had a very weak HEDT offering over the past few years with their 14 nm Cascade Lake processors and X299 chipset where the flagship Core i9-10980XE offered just 18 cores. Intel appears to be preparing to launch an updated HEDT offering in Q2 2022 with 10 nm Sapphire Rapids processors and a new W790 chipset. The new W790 chipset may launch alongside Raptor Lake which is expected to support the Z790 chipset. We still have a while until these products launch with Intel not yet having released their Alder Lake predecessors while AMD is expected to announce Threadripper 5000 in the coming months.

Intel's Lisa Spelman, corporate vice president and general manager of the Xeon and Memory Group at Intel Corporation, has yesterday published a blog post talking about Intel's next-generation server platform codenamed Sapphire Rapids. The SPR platform is Intel's biggest step-up in the server processor space, and it is the exact CPU that will power the Aurora exascale supercomputer. Besides improvements to the CPU microarchitecture, the platform itself is bringing many benefits with it as well. It will use the latest industry protocols like DDR5 and PCIe 5.0. This is making a strong combination designed even for exascale supercomputers to be powered by this processor. However, the availability of this CPU was a bit of a mystery until yesterday. Below, you can see the quote from Ms. Lisa Spelman about the availability of said processors.

Lisa SpelmanDemand for Sapphire Rapids continues to grow as customers learn more about the benefits of the platform. Given the breadth of enhancements in Sapphire Rapids, we are incorporating additional validation time prior to the production release, which will streamline the deployment process for our customers and partners. Based on this, we now expect Sapphire Rapids to be in production in the first quarter of 2022, with ramp beginning in the second quarter of 2022.

Intel today, in its 2021 International Supercomputing Conference presentation, revealed that certain next-generation Xeon "Sapphire Rapids" SKUs come with on-package high-bandwidth memory (HBM). Given the context of its presentation, these could be special SKUs designed for high-density HPC setups, in which the processor package includes certain amount of "PMEM" (package memory), besides the processor's 8-channel DDR5 memory interface.

The size of the HBM PMEM, and its position in the memory hierarchy, were detailed, too. Given its high-density applications, PMEM may not serve as a victim cache for the processor, but rather be capable of serving as main memory, with none of the DDR5 DRAM channels populated with DIMMs. On machines with DIMMs, the PMEM will serve as a victim cache for the processor's on-die last-level cache, accelerating the memory I/O. "The next-generation of Intel Xeon Scalable processors (code-named "Sapphire Rapids) will offer integrated High Bandwidth Memory (HBM), providing a dramatic boost in memory bandwidth and a significant performance improvement for HPC applications that operate memory bandwidth-sensitive workloads. Users can power through workloads using just High Bandwidth Memory or in combination with DDR5," says Intel.

At the 2021 International Supercomputing Conference (ISC) Intel is showcasing how the company is extending its lead in high performance computing (HPC) with a range of technology disclosures, partnerships and customer adoptions. Intel processors are the most widely deployed compute architecture in the world's supercomputers, enabling global medical discoveries and scientific breakthroughs. Intel is announcing advances in its Xeon processor for HPC and AI as well as innovations in memory, software, exascale-class storage, and networking technologies for a range of HPC use cases.

"To maximize HPC performance we must leverage all the computer resources and technology advancements available to us," said Trish Damkroger, vice president and general manager of High Performance Computing at Intel. "Intel is the driving force behind the industry's move toward exascale computing, and the advancements we're delivering with our CPUs, XPUs, oneAPI Toolkits, exascale-class DAOS storage, and high-speed networking are pushing us closer toward that realization."

Thanks to the information coming from Yuuki_Ans, a person which has been leaking information about Intel's upcoming 4th generation Xeon Scalable processors codenamed Sapphire Rapids, we have the first die shots of the Sapphire Rapids processor and its delidded internals to look at. After performing the delidding process and sanding down the metal layers of the dies, the leaker has been able to take a few pictures of the dies present on the processor. As the Sapphire Rapids processor uses multi-chip modules (MCM) approach to building CPUs, the design is supposed to provide better yields for Intel and give the 10 nm dies better usability if defects happen.

In the die shots, we see that there are four dies side by side, with each die featuring 15 cores. That would amount to 60 cores present in the system, however, not all of the 60 cores are enabled. The top SKU is supposed to feature 56 cores, meaning that there would be at least four cores disabled across the configuration. This gives Intel flexibility to deliver plenty of processors, whatever the yields look like. The leaked CPU is an early engineering sample design with a low frequency of 1.3 GHz, which should improve in the final design. Notably, as Sapphire Rapids has SKUs that use in-package HBM2E memory, we don't know if the die configuration will look different from the one pictured down below.

Marvell today announced its new Bravera SC5 controller family, bringing unprecedented performance, best-in-class efficiency, and leading security features to address ever-expanding workloads in the cloud. The massive amount of data to be processed in cloud data centers is driving demand for faster and higher bandwidth storage in these environments. Marvell's Bravera SC5 SSD controllers address the critical requirements for scalable, containerized cloud storage infrastructure. By enabling the highest performing flash storage solutions, Marvell's controllers are poised to be the foundation for data centers that offer ultra-low latency, real-time applications while also providing cost-optimized, cloud-scale capacity.

As the industry's first SSD controllers to support PCIe 5.0 and NVMe 1.4b, Marvell's Bravera SC5 doubles the performance compared to PCIe 4.0 SSDs. This contributes to accelerated workloads and reduced latency, dramatically improving the user experience. In order to meet cloud service providers' stringent security requirements to ensure users' data is safe and protected, the controllers offer FIPS-compliant root of trust (RoT), AES 256-bit encryption and multi-key revocation. The new controllers are the first with a hardware-based Elastic SLA Enforcer to assure quality of service (QoS) and provide metering capabilities per customer to increase overall storage efficiency and utilization while lowering total cost of ownership (TCO).

Intel's upcoming Xeon "Sapphire Rapids" processors which debut in the second half of 2021, will feature up to 80 "Golden Cove" CPU cores, and not the previously rumored "Willow Cove." This was clarified by an Intel developer in a Linux Kernel code e-mail chain. "Golden Cove" CPU cores are more advanced than the "Willow Cove" cores found in current-generation Intel products, such as the client "Tiger Lake" processors. Intel stated that "Golden Cove" introduces an IPC gain over "Willow Cove" (expressed as "ST perf"), increased AI inference performance from an updated GNI component, "network and 5G perf," which is possibly some form of network stack acceleration, and additional security features.

Over in the client segment, the 12th Gen Core "Alder Lake" processor debuts a client variant of "Golden Cove." The "Alder Lake-S" silicon features eight "Golden Cove" cores serving as the "big" performance cores, next to eight "little" low-power "Gracemont" cores. The client- and server implementations of "Golden Cove" could differ mainly in the ISA, with the client chip receiving a slightly skimmed AVX-512 and DLBoost instruction-sets, with only client-relevant instructions. The server variant, in addition being optimized for a high core-count multi-core topology; could feature a more substantial AVX-512 and DLBoost implementation relevant for HPC use-cases.

Intel will detail its 12th Gen Core "Alder Lake" client and "Sapphire Rapids" server CPU microarchitectures at the Hot Chips 33 conclave, this August. In fact, Intel's presentation leads the CPU sessions on the opening day of August 23. "Alder Lake" will be the session opener, followed by AMD's presentation of the already-launched "Zen 3," and IBM's 5 GHz Z processor powering its next-gen mainframes. A talk on Xeon "Sapphire Rapids" follows this. Hot Chips is predominantly an engineering conclave, where highly technical sessions are presented by engineers from major semiconductor firms; and so the sessions on "Alder Lake" and "Sapphire Rapids" are expected to be very juicy.

"Alder Lake" is Intel's attempt at changing the PC ecosystem by introducing hybrid CPU cores, a concept introduced to the x86 machine architecture with "Lakefield." The processor will also support next-generation I/O, such as DDR5 memory. The "Sapphire Rapids" server CPU microarchitecture will see an increase in CPU core counts, next-gen I/O such as PCI-Express 5.0, CXL 1.1, DDR5 memory, and more.

Today, Lenovo in partnership with Intel has announced that Leibniz Supercomputing Centre (LRZ) is building a supercomputer powered by Intel's next-generation technologies. Specifically, the supercomputer will use Intel's Sapphire Rapids CPUs in combination with the highly-teased Ponte Vecchio GPUs to power the applications running at Leibniz Supercomputing Centre. Along with the various processors, the LRZ will also deploy Intel Optane persistent memory to process the huge amount of data the LRZ has and is producing. The integration of HPC and AI processing will be enabled by the expansion of LRZ's current supercomputer called SuperMUG-NG, which will receive an upgrade in 2022, which will feature both Sapphire Rapids and Ponte Vecchio.

Mr. Raja Koduri, Intel graphics guru, has on Twitter teased that this supercomputer installment will represent a combination of Sapphire Rapids, Ponte Vecchio, Optane, and One API all in one machine. The system will use over one petabyte of Distributed Asynchronous Object Storage (DAOS) based on the Optane technologies. Then, Mr. Koduri has teased some Ponte Vecchio eye candy, which is a GIF of tiles combining to form a GPU, which you can check out here. You can also see some pictures of Ponte Vecchio below.

Intel's upcoming Xeon "Sapphire Rapids" enterprise processor come come with CPU core-counts as high as 80, according to the latest round of photo-leaks. An earlier article predicted the chip cram up to 56 cores alongside on-package HBM. The processor reportedly features up to 80 cores, spread across four 20-core chiplets. Unlike on the latest AMD EPYC processor, there doesn't appear to be a centralized I/O controller die. This particular processor is based in the LGA4189 package, which features additional pins compared to the LGA4577-X socket from the 56-core leak. The newer socket has additional pins that enable next-gen I/O, which include PCI-Express Gen 5.0, and CXL 1.1 interface.