MediaTek today launched the Dimensity 9200, its latest 5G chipset powering the next era of flagship smartphones. Boasting extreme performance and intelligent power efficiency, the new SoC brings immersive all-day gaming experiences, ultra-sharp image capturing and support for both mmWave 5G and sub-6 GHz connectivity to consumers around the globe.

"MediaTek's Dimensity 9200 combines ultimate performance with significant power savings, extending battery life and keeping smartphones cool," said JC Hsu, Corporate Vice President and General Manager of MediaTek's wireless communications business unit at MediaTek. "With notably brighter image capturing and improved gaming speeds, along with the latest display enhancements, the Dimensity 9200 will bring new possibilities for next-gen smartphones that come in a variety of stylish and foldable form factors."

Over the past few weeks, the legal dispute between Arm Ltd. and Qualcomm Inc. has been warming up the eyes of the entire tech community. However, as per the latest court filing, Arm could change its licensing strategy and shift its whole business model into a new direction that would benefit the company directly. Currently, the company provides the intellectual property (IP) that chip makers can use and add to designs mixed with other IPs and custom in-house solutions. That is how the world of electronics design (EDA) works and how many companies operate. However, in the Qualcomm-Arm legal battle, Qualcomm's counterclaim has brought new light about Arm's plans for licensing its hardware designs past 2024.

According to Dylan Patel of SemiAnalysis, who examined court documents, Arm will reportedly change terms to use its IP where the use of other IP mixed with Arm IP is prohibited. If a chip maker plans to use Arm CPU IP, they must also use Arm's GPU/NPU/ISP/DSP IPs. This would result in devices that utilize every design the UK-based designer has to offer, and other IP makers will have to exclude their designs from the SoC. By doing this, Arm directly stands against deals like the Samsung-AMD deal, where AMD provides RDNA GPU IP and would force Samsung to use Arm's Mali GPU IP instead. This change should take effect in 2025 when every new license agreement has to comply with new rules.

Alphawave IP (LSE: AWE), a global leader in high-speed connectivity for the world's technology infrastructure, today announced the successful tapeout of its ZeusCORE100 1-112 Gbps NRZ/PAM4 Serialiser-Deserialiser ("SerDes"), Alphawave's first testchip on TSMC's most advanced N3E process. Alphawave IP will be exhibiting this new product alongside its complete portfolio of high-performance IP, chiplet, and custom silicon solutions at the TSMC OIP Forum on October 26 in Santa Clara, CA as the Platinum sponsor.

ZeusCORE100 is Alphawave's most advanced multi-standard-SerDes, supporting extra-long channels over 45dB and the most requested standards such as 800G Ethernet, OIF 112G-CEI, PCIe GEN6, and CXL 3.0. Attendees will be able to visit the Alphawave booth and meet the company's technology experts including members of the recently acquired OpenFive team. OpenFive is a longstanding partner of TSMC through the OIP Value Chain Aggregator (VCA) program. OpenFive is one of a select few companies with an idea-to-silicon methodology in TSMC's latest technologies, and advanced packaging capabilities, enabling access to the most advanced foundry solution available with the best Power-Performance-Area (PPA). With Alphawave's industry-leading IP portfolio and the addition of OpenFive's capabilities, designers can create systems on a chip (SoCs) that pack more compute power into smaller form factors for networking, AI, storage, and high-performance computing (HPC) applications.

In December of 2021, we covered the appearance of Russia's home-grown Baikal-S processor, which has 48 cores based on Arm Cortex-A75 cores. Today, thanks to the famous chip photographer Fritzchens Fritz, we have the first die shows that show us exactly how Baikal-S SoC is structured internally and what it is made up of. Manufactured on TSMC's 16 nm process, the Baikal-S BE-S1000 design features 48 Arm Cortex-A75 cores running at a 2.0 GHz base and a 2.5 GHz boost frequency. With a TDP of 120 Watts, the design seems efficient, and the Russian company promises performance comparable to Intel Skylake Xeons or Zen1-based AMD EPYC processors. It also uses a home-grown RISC-V core for management and controlling secure boot sequences.

Below, you can see the die shots taken by Fritzchens Fritz and annotated details by Twitter user Locuza that marked the entire SoC. Besides the core clusters, we see that a slum of cache connects everything, with six 72-bit DDR4-3200 PHYs and memory controllers surrounding everything. This model features a pretty good selection of I/O for a server CPU, as there are five PCIe 4.0 x16 (4x4) interfaces, with three supporting CCIX 1.0. You can check out more pictures below and see the annotations for yourself.

Yesterday Intel announced its 13th generation Raptor Lake processor lineup. The top-of-the-line model, Core i9-13900KS, features eight P-cores and 16 E-cores for a total of 24 cores in the SoC. However, that may not represent the maximum for Raptor Lake, as there appears to be another segment equipped with a Raptor Lake processor with 34 cores. According to findings of Tom's Hardware, the Intel Innovation event in San Jose had a surprise for everyone, as there was a booth to display Raptor Lake silicon wafers. After closer examination, the wafer had cutouts for dies that contained as many as 34 cores.

With all cores being the same size, it is assumed that those are P-cores interconnected on a mesh, unlike the traditional ring bus that the rest of Raptor Lake processors use. On the back of the wafer was a label stating, "Raptor Lake-S, 34 core". This suggests that the CPU is perhaps a part of the HEDT offerings that Intel will soon update with the 13th generation designs and that the company showcased a production wafer for those SKUs. We expect to hear more about this unknown 34-core configuration sometime in the future as the new Intel Core generation begins its rollout.

According to TrendForce research, due to steady weakening of overall demand for consumer electronics, inventory pressure has increased among downstream distributors and brands. Although there are still sporadic shortages of specific components, the curtain has officially fallen on a two-year wave of shortages in general, and brands have gradually suspended stocking in response to changes in market conditions. However, stable demand for automotive and industrial equipment is key to supporting the ongoing growth of foundry output value. At the same time, since the creation of a marginal amount of new capacity in 2Q22 led to growth in wafer shipments and a price hike for certain wafers, this drove output value among top ten foundries to reach US$33.20 billion in 2Q22. Quarterly growth fell to 3.9% on a weakening consumer market.

A prelude to inventory correction was officially revealed in 3Q22. In addition to intensifying severity in the initial wave of order slashing for LDDI/TDDI, and TV SoC, diminishing order volume also extended to non-Apple smartphone APs and peripheral IC PMIC, CIS, and consumer electronics PMICs, and mid-to-low-end MCUs, posing a challenge for foundry capacity utilization. However, the launch of the new iPhone in 3Q22 is expected to prop up a certain amount of stocking momentum for the sluggish market. Therefore, top ten foundry revenue in 3Q22 is expected to maintain a growth trend driven by high-priced processes and quarterly growth rate is expected to be slightly higher than in 2Q22.

According to Dylan Patel of SemiAnalysis sources, Apple is moving its embedded cores from Arm to RISC-V. In Apple's Silicon designs, there are far more cores than the main ones that power the operating system and end-user applications. For example, embedded cores are present, and there are 30+ in M1 SoCs responsible for all kinds of workloads not related to the operating system. These tasks are usually associated with other functions such as WiFi/BlueTooth, ThunderBolt retiming, touchpad control, NAND chips having their own core, etc. They run their own firmware and power everything around the central cores that run the OS, so the whole SoC functions appropriately.

It appears that a lot of these cores are based on Arm M-series or lower-end A-series IP that Apple is currently looking to replace with RISC-V. Given that a large portion of software runs on the main big.LITTLE configuration, other secondary SoC tasks can migrate to a different ISA like RISC-V, with a small firmware adjustment. Given that these cores can be placed with custom IPs, Apple would save licensing fees if custom RISC-V cores were used. Additionally, developing firmware for these cores at an Apple engineering team size shouldn't be a problem. Of course, we have no information about when these custom cores will appear inside Apple Silicon. Even when they are used, no formal announcement is expected given that the main cores remain to be powered by Arm ISA, with everything else invisible to the end-user.

Kinara, Inc., developer of unrivaled Edge AI solutions that accelerate and optimize real-time decision making, today announced that it has partnered with Arcturus Networks Inc., provider of edge AI analytics and enablement for smart city applications, to help customers deliver high-performance, cost-optimized AI solutions.

The partnership combines the Kinara Ara-1 Edge AI processor with Arcturus Brinq edge AI and vision analytics software to drive leading-edge detection, tracking and characterization solutions. The partnership delivers the critical software and hardware platforms required by OEMs to build sophisticated real-time edge applications for public safety, transportation, healthcare, retail, and industrial markets. For example, Kinara and Arcturus can deliver a real-time solution for road condition monitoring, allowing public transportation buses retrofitted with smart cameras to detect road obstructions such as potholes and report them directly to city operations.

Intel has announced the availability of its 12th Gen Intel Core SoC processors for IoT Edge. Representing a new lineup of purpose-built edge products optimized for Internet of Things (IoT) applications, this first-of-its-kind socketed system-on-chip (SoC) delivers high performance integrated graphics and media processing for visual compute workloads, a compact footprint to enable smaller innovative form factor designs, and a wide operating thermal design power (TDP) that enables fanless designs and helps customers achieve product sustainability goals.

"As the digitization of business processes continues to accelerate—fueled by workforce demand, supply chain constraints and changing consumer behavior—the amount of data created at the edge and the need for it to be processed and analyzed locally continues to explode. Intel understands the challenges that businesses face—across a wide range of vertical industries—and is committed to help them continue to deliver innovative use cases," said Jeni Panhorst, Intel vice president and general manager of the Network and Edge Compute Division.

Microsoft is reportedly planning to merge its ARM-powered Surface Pro X brand into the main Surface Pro line starting with the upcoming Surface Pro 9. This would see the Surface Pro 9 being offered with the upcoming Microsoft SQ3 processor which is derived from the Snapdragon 8cx Gen3. Microsoft has previously announced a desktop ARM developer kit codenamed "Project Volterra" featuring the Snapdragon 8cx Gen3 SoC and a neural processing unit that should offer similar performance. The Surface Pro 9 is also expected to gain 5G connectivity when it is announced alongside updated Surface Studio, and Surface Laptop products in the coming weeks.

MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS' eVocore is being incorporated into the new Intel Pathfinder for RISC-V, a platform designed to deliver new capabilities for pre-silicon development. Intel Pathfinder allows new ways for System-on-a-Chip (SoC) architects and system software developers to define new products and pursue pre-silicon software development on RISC-V.

"MIPS is thrilled to be part of the Intel Pathfinder for RISC-V platform, providing high performance cores with support for multi-cluster, multi-core and multi-threading to accelerate innovation," said Desi Banatao, MIPS CEO. "These multiprocessors have unique features and a high level of scalability that make them ideal for compute-intensive tasks across a broad range of markets and applications."

Committed to providing innovative embedded solutions, AAEON has introduced the RBX-I2000, its first autonomous robot controller. The RBX-I2000 utilizes hardware-integrated time synchronization to obtain a substantial improvement on existing outdoor autonomous mobile robot technology, being the first of its kind to do so.

Powering its sophisticated mechanism is the 11th Generation Intel Core i7/i5/i3/Celeron Processor SoC, which boasts 4 cores and 8 threads for accurate algorithmic processing. Such an advanced processing unit means the RBX-I2000 is equipped with the power necessary for hardware-based time synchronization, which is channeled via an I/O featuring four 1PPS and ToD output ports to improve sensor fusion on two connectors.

Based on media reports out of Taiwan, TSMC seems to have plenty of customers lined up for its 3 nm node, with Apple being the first customer out the gates when production starts sometime next month. However, TSMC is only expected to start the production with a mere 1,000 wafer starts a month, which seems like a very low figure, especially as this is said to remain unchanged through all of Q4. On the plus side, yields are expected to be better than the initial 5 nm node yields. Full-on mass production for the 3 nm node isn't expected to happen until the second half of 2023 and TSMC will also kick off its N3E node sometime in 2023.

Apart from Apple, major customers for the 3 nm node include AMD, Broadcom, Intel, MediaTek, NVIDIA and Qualcomm. Contrary to earlier reports by TrendForce, it appears that TSMC will continue its rollout of the 3 nm node as previously planned. Apple is expected to produce the A17 smartphone and tablet SoC, as well as advanced versions of the M2, as well as the M3 laptop and desktop processors on the 3 nm node. Intel is still said to be producing its graphics chiplets with TSMC, with the potential for GPU and FPGA products in the future. There's no word on what the other customers are planning to produce on the 3 nm node, but MediaTek and Qualcomm are obviously looking at using the node for future smartphone and tablet SoCs, with AMD and NVIDIA most likely aiming for upcoming GPUs and Broadcom for some kind of HPC related hardware.

The Chinese technology giant, SMIC, has managed to advance its semiconductor manufacturing technology and shipped the first 7 nm silicon manufactured on China's soil. According to analyst firm TechInsights, who examined the 7 nm Bitcoin mining SoC made for MinerVa firm, there are doubts that SMIC 7 nm process is somewhat similar to TSMC's 7 nm process. Despite having no access to advanced semiconductor manufacturing tools, and US restrictions placed around it, SMIC has managed to produce what resembles an almost perfect 7 nm node. This could lead to a true 7 nm logic and memory bitcells sometimes in the future, as the node advances in SMIC's labs.

Having done an in-depth die analysis, the TechInsights report indicates that TSMC, Intel, and Samsung have a more advanced 7 nm node and are two nodes ahead of the Chinese SMIC. The results are not great regarding the economics and yield of this SMIC 7 nm process. While we have no specific data, the report indicates that the actual working chips made with older DUV tools are not perfect. This is not a problem for the Chinese market as it seeks independence from Western companies and technology. However, introducing a China-made 7 nm chip is more critical as it shows that the country can manufacture advanced nodes with restrictions and sanctions in place. The MinerVa SoC die and the PCB that houses those chips are pictured below.

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today announced that it has successfully developed a second generation of its pioneering SmartSSD. The new proprietary computational storage incorporates data processing functionality within a high-performance SSD. Unlike existing SSDs, Samsung's SmartSSD can process data directly, thereby minimizing data transfers between the CPU, GPU and RAM. This technology can avoid the bottlenecks that often occur when moving data between storage devices and CPUs, resulting in markedly improved system performance and much higher energy efficiency.

The SmartSSD is playing an increasingly important role, especially with the growth of next-generation technologies such as AI, machine learning and 5G/6G, which require large amounts of data processing. Leveraging software and intellectual property (IP) developed by customers, along with in-built Arm cores, Samsung's second-generation SmartSSD enables much more efficient data processing. Compared to conventional data center solid-state drives, processing time for scan-heavy database queries can be slashed by over 50%, energy consumption by up to 70% and CPU utilization by up to 97%.

The next-generation of UP Board, a credit card-sized SBC (single board computer) was unveiled, revealing a mighty SoC at the helm, the Intel Pentium Silver, Celeron, or Atom "Apollo Lake." The UP 4000 is suitable for most embedded system projects in which you require the x86-64 machine architecture. Competing SBCs tend to be based on Arm or RISC-V architectures. The 85 mm x 56 mm board puts out an Ethernet interface, three 5 Gbps USB 3.0 ports, a type-C USB 3.0 port, and an HDMI display output, besides GPIO. The SoC is hardwired to 8 GB of single-channel DDR4 memory, 64 GB of eMMC storage, Available now for pre-order, the UP Board starts at $116.

According to TrendForce investigations, foundries have seen a wave of order cancellations with the first of these revisions originating from large-size Driver IC and TDDI, which rely on mainstream 0.1X μm and 55 nm processes, respectively. Although products such as MCU and PMIC were previously in short supply, foundries' capacity utilization rate remained roughly at full capacity through their adjustment of product mix. However, a recent wave cancellations have emerged for PMIC, CIS, and certain MCU and SoC orders. Although still dominated by consumer applications, foundries are beginning to feel the strain of the copious order cancellations from customers and capacity utilization rate has officially declined.

Looking at trends in 2H22, TrendForce indicates, in addition to no relief from the sustained downgrade of driver IC demand, inventory adjustment has begun for smartphones, PCs, and TV-related peripheral components such as SoCs, CIS, and PMICs, and companies are beginning to curtail their wafer input plans with foundries. This phenomenon of order cancellations is occurring simultaneously in 8-inch and 12-inch fabs at nodes including 0.1X μm, 90/55 nm, and 40/28 nm. Not even the advanced 7/6 nm processes are immune.

Mobileye, an Intel company, has launched the EyeQ Kit - its first software development kit (SDK) for the EyeQ system-on-chip that powers driver-assistance and future autonomous technologies for automakers worldwide. Built to leverage the powerful and highly power-efficient architecture of the upcoming EyeQ 6 High and EyeQ Ultra processors, EyeQ Kit allows automakers to utilize Mobileye's proven core technology, while deploying their own differentiated code and human-machine interface tools on the EyeQ platform.

"EyeQ Kit allows our customers to benefit from the best of both worlds — Mobileye's proven and validated core technologies, along with their own expertise in delivering unique driver experiences and interfaces. As more core functions of vehicles are defined in software, we know our customers will want the flexibility and capacity they need to differentiate and define their brands through code."
- Prof. Amnon Shashua, Mobileye president and chief executive officer

DeepComputing and Xcalibyte today opened pre-orders for the industry's first native RISC-V development laptop. The hotly anticipated ROMA development platform features an unannounced quad-core RISC-V processor with a companion NPU/GPU for the fastest, seamless RISC-V native software development available.

"Native RISC-V compile is a major milestone," said Mark Himelstein, Chief Technology Officer for RISC-V International. "The ROMA platform will benefit developers who want to test their software running natively on RISC-V. And it should be easy to transfer code developed on this platform to embedded systems."

Imagination Technologies announces IMG RTXM-2200, its first real-time embedded RISC-V CPU, a highly scalable, feature-rich, 32-bit embedded solution with a flexible design for a wide range of high-volume devices. IMG RTXM-2200 is one of the first commercial cores in Imagination's Catapult CPU family, previously announced in December 2021. Accelerating the expansion of its RISC-V offering, Imagination's IMG RTXM-2200 can be integrated into complex SoCs for a range of applications including networking solutions, packet management, storage controllers, and sensor management for AI cameras and smart metering. Together with its market-leading GPU and AI accelerator IP, Imagination's new CPU cores offer customers access to innovative heterogeneous solutions.

This real-time embedded core features up to 128 KB of tightly coupled memories (both instruction and data) for deterministic response and Level 1 cache sizes of up to 128 KB for robust performance. The new CPU offers a range of floating-point formats including single-precision and bfloat16. The latter enables manufacturers to deploy AI applications through this core without the need for an additional chip. This reduces silicon area, for a cost-effective and optimised design in AI cameras and smart metering applications.

MediaTek today announced the Dimensity 9000+, an enhancement to the company's top-of-the-line 5G smartphone chipset. This new high-end offering delivers a boost in performance over the Dimensity 9000 to make the next generation of flagship smartphones even more powerful and efficient.

The new Dimensity 9000+ system-on-chip (SoC) integrates Arm's v9 CPU architecture with a 4 nm octa-core process, combining one ultra-Cortex-X2 core operating at up to 3.20 GHz (compared to 3.05 GHz with the Dimensity 9000) with three super Cortex-A710 cores and four efficiency Cortex-A510 cores. The advanced CPU architecture and Arm Mali-G710 MC10 graphics processor built into the new chipset provide more than a 5% boost in CPU performance and more than 10% improvement in GPU performance.

With the launch of Apple Silicon for Mac computers, Apple has established itself as a great user of the Arm instruction set. Starting with M1, the company released an entirely new family of products running Apple Silicon. Today, thanks to the research of Strategy Analytics company, we have information that Apple is capturing as much as 90% of the revenue share present in the Arm PC market. The Arm PC market is a tiny subset of the entire PC market, mainly equipped with one-off Windows-on-Arm devices, Chromebook PCs, and Apple Macs. With the naturally low prices of the remaining Arm PCs, Apple Arm PCs offer a relatively high price point and a much more incredible selection of products.

On the global scale, Arm PCs now account for 9% of the total PC market share, where x86 vendors are dominating the field. "Apple's M-series family of processors set the benchmark and gave Apple a 2-3-year lead over the rest of the Arm-based PC processor vendors. Qualcomm captured just 3% revenue share in the Arm-based notebook PC processor market in 2021 and lags Apple in CPU performance," said Sravan Kundojjala, Director of Handset Component Technologies service at Strategy Analytics. This points to a particular case of Apple's better product and feeding the demand with higher-performing processors. Qualcomm's acquisition of Nuvia should yield different results in the coming years, as the new IP is yet to appear in Qualcomm SoCs.

Researchers from Università di Bologna and CINECA, the largest supercomputing center in Italy, have been playing with the concept of developing a RISC-V supercomputer. The team has laid the grounds for the first-ever implementation that demonstrates the capability of the relatively novel ISA to run high-performance computing. To create a supercomputer, you need pieces of hardware that seem like Lego building blocks. Those are called clusters, made from a motherboard, processor, memory, and storage. Italian researchers decided to try and use something different than Intel/AMD solution to the problem and use a processor based on RISC-V ISA. Using SiFive's Freedom U740 SoC as the base, researchers named their RISC-V cluster "Monte Cimone."

Monte Cimone features four dual-board servers, each in a 1U form factor. Each board has a SiFive's Freedom U740 SoC with four U74 cores running up to 1.4 GHz and one S7 management core. In total, eight nodes combine for a total of 32 RISC-V cores. Paired with 16 GB of 64-bit DDR4 memory operating at 1866s MT/s, PCIe Gen 3 x8 bus running at 7.8 GB/s, one gigabit Ethernet port, USB 3.2 Gen 1 interfaces, the system is powered by two 250 Watt PSUs to support future expansion and addition of accelerator cards.

Intel's semiconductors nodes have been quite controversial with the arrival of the 10 nm design. Years in the making, the node got delayed multiple times, and only recently did the general public get the first 10 nm chips. Today, at IEEE's annual VLSI Symposium, we get more details about Intel's upcoming nodes, called Intel 4. Previously referred to as a 7 nm process, Intel 4 is the company's first node to use EUV lithography accompanied by various technologies. The first thing when a new process node is discussed is density. Compared to Intel 7, Intel 4 will double the transistor count for the same area and enable 20% higher performing transistors.

Looking at individual transistor size, the new Intel 4 node represents a very tiny piece of silicon that is even smaller than its predecessor. With a Fin Pitch of 30 nm, Contact Gate Poly Pitch of 50 nm between gates, and Minimum Metal Pitch (M0) of 50 nm, the Intel 4 transistor is significantly smaller compared to the Intel 7 cell, listed in the table below. For scaling, Intel 4 provides double the number of transistors in the same area compared to Intel 7. However, this reasoning is applied only to logic. For SRAM, the new PDK provides 0.77 area reduction, meaning that the same SoC built on Intel 7 will not be half the size of Intel 4, as SRAM plays a significant role in chip design. The Intel 7 HP library can put 80 million transistors on a square millimeter, while Intel 4 HP is capable of 160 million transistors per square millimeter.

Intel is preparing to launch its 13th generation of desktop processors codenamed Raptor Lake. Succeeding Alder Lake, the 13th gen design will implement up to eight P-cores with 16 E-cores manufactured on Intel's improved 7+ technology node. Today, we got a performance preview from SiSoftware that has collected SiSoftware Sandra database scores of Intel Core i9-13900 Raptor Lake-S processor. They present an overview of a few benchmarks. Firstly, the SoC features 36 MB of unified L3 cache versus 30 MB in Alder Lake. With DDR5 memory running up to 5600 MT/s and PCIe 5.0, the SoC features the latest IO and memory standards. The big P-cores now lack AVX-512 and feature 2 MB of L2 cache per core. We see 4 MB of L2 cache for a cluster of small E-cores. An exciting addition to E-cores is the AVX/AVX2 support, which is a first for Atom cores.

Regarding testing, the author has collected a few tests that seemed appropriate to compare to the equivalent Alder Lake model. Starting with ALU/FPU tests that benchmark basic arithmetic tasks, Raptor Lake delivered 33% to 50% improvement over Alder Lake. The Raptor Lake design achieved this with 3.7 GHz P-Core and 2.76 GHz E-Core frequency. In vectorized and SIMD tests, the 13th gen design showed only 5% to 8% improvement over the previous generation. For more benchmarks and accurate results, we have to wait for TechPowerUp's test, which will be coming on the release day.