AMD's upcoming server processor, the 5th Gen EPYC "Turin," has been pictured as an engineering sample is probably being evaluated by the company's data-center or cloud customers. The processor has a mammoth core-count of 192-core/384-thread in its high-density cloud-focused variant that uses "Zen 5c" CPU cores. Its regular version that uses larger "Zen 5" cores that can sustain higher clock speeds, also comes with a fairly high core-count of 128-core/256-thread, up from the 96-core/192-thread of the "Zen 4" based EPYC "Genoa."

The EPYC "Turin" server processor based on "Zen 5" comes with an updated sIOD (server I/O die), surrounded by as many as 16 CCDs (CPU complex dies). AMD is expected to build these CCDs on the TSMC N4P foundry node, which is a more advanced version of the TSMC N4 node the company currently uses for its "Phoenix" client processors, and the TSMC N5 node it uses for its "Zen 4" CCD. TSMC claims that the N4P node offers an up to 22% improvement in power efficiency over N5, as well as a 6% increase in transistor density. Each of the "Zen 5" CCDs is confirmed to have 8 CPU cores sharing 32 MB L3 cache memory. A total of 16 such CCDs add up to the processor's 128-core/256-thread number. The high-density "Turin" meant for cloud data-centers, is a whole different beast.

AMD in its Ryzen 8040 series "Hawk Point" mobile processors announcement made the first mention of XDNA 2, its next-generation on-chip neural processing unit (NPU) architecture. Above all, the XDNA 2 NPU is expected to introduce an over 3 times improvement in performance over the first generation XDNA NPU powering the Ryzen 7040 series "Phoenix" processor. XDNA 2 is making its debut with AMD's next-generation Ryzen "Strix Point" mobile processor that the company looks to launch in 2024. While "Phoenix" offers 10 TOPS of NPU performance, AMD mentions an "over 3 times" performance improvement, which probably puts this figure at 32 TOPS for "Strix Point."

The "Strix Point" mobile processor is rumored to debut faster "Zen 5" CPU cores, a possible CPU core count increase to 12, and a much more powerful iGPU based on the updated RDNA 3.5 graphics architecture, with some SKUs expected to feature CU counts as high as 32, and designed to square off against the iGPU of the Apple M3 Max processor. Besides "Zen 5" CPU cores and RDNA 3.5 iGPU, we now know that even the NPU gets an overhaul with this XDNA 2 announcement, and a possible 32 TOPS NPU performance.

A curious piece of marketing material on the Chiphell forum has sent ripples through the tech community, featuring what appears to be an Alienware desktop equipped with an unannounced AMD Ryzen 9000-series processor. The authenticity of this flyer is up for debate, with possibilities ranging from a simple typo by Alienware to a fabricated image, or it could even suggest that AMD is on the cusp of unveiling its next-generation Ryzen CPUs for desktop PCs. While intrigue is high, it's important to approach such revelations cautiously, with a big grain of salt. AMD's existing roadmap points toward a 2024 release for its Zen 5-based Ryzen desktop processors and EPYC server CPUs, which casts further doubt on the Ryzen 9000 series appearing ahead of schedule.

We have to wait for AMD's major upcoming events, including the "Advancing AI" event on December 6, where the company will showcase how its partners and AMD use AI for applications. Next, we hope to hear from AMD about upcoming events such as CES in January and Computex in May, but we don't have any official information on product launches in the near term. If the company is preparing anything, the Alienware flyer pictured below should indicate it, if the source is confirmed. However, the doubt remains, and we should be skeptical of its truthfulness.

With Windows 11 23H2 setting the stage for increased prevalence of AI in client PC use cases, the new hardware battleground between AMD and its rivals Intel, Apple, and Qualcomm, will be in equipping their mobile processors with sufficient AI acceleration performance. AMD already introduced accelerated AI with the current "Phoenix" processor that debuts Ryzen AI, and its Xilinx XDNA hardware backend that provides a performance of up to 16 TOPS. This will see a 2-3 fold increase with the company's 2024-25 mobile processor lineup, according to a roadmap leak by "Moore's Law is Dead."

At the very top of the pile, in a product segment called "ultimate compute," which consists of large gaming notebooks, mobile workstations, and desktop-replacements; the company's current Ryzen 7045 "Dragon Range" processor will continue throughout 2024. Essentially a non-socketed version of the desktop "Raphael" MCM, "Dragon Range" features up to two 5 nm "Zen 4" CCDs for up to 16 cores, and a 6 nm cIOD. This processor lacks any form of AI acceleration. In 2025, the processor will be succeeded with "Fire Range," a similar non-socketed, mobile-friendly MCM that's derived from "Granite Ridge," with up to two 4 nm "Zen 5" CCDs for up to 16 cores; and the 6 nm cIOD. What's interesting to note here, is that the quasi-roadmap makes no mention of AI acceleration for "Fire Range," which means "Granite Ridge" could miss out on Ryzen AI acceleration from the processor. Modern discrete GPUs from both NVIDIA and AMD support AI accelerators, so this must have been AMD's consideration to exclude an XDNA-based Ryzen AI accelerator on "Fire Range" and "Granite Ridge."

"Strix Point" is the codename for AMD's next-generation mobile processor succeeding the current Ryzen 7040 series "Phoenix." More details of the processor emerged thanks to "All The Watts!!" on Twitter. The CPU of "Strix Point" will be heterogenous, in that it will feature two different kinds of CPU cores, but with essentially the same ISA and IPC. It is rumored that the processor will feature 4 "Zen 5" CPU cores, and 8 "Zen 5c" cores.

Both core types feature an identical IPC, but the "Zen 5" cores can hold onto higher boost frequencies, and have a wider frequency band, than the "Zen 5c" cores. From what we can deduce from the current "Zen 4c" cores, "Zen 5c" cores aren't strictly "efficiency" cores, as they still offer the full breadth of core ISA as "Zen 5," including SMT. In its maximum configuration, "Strix Point" will hence be a 12-core/24-thread processor. The two CPU core types sit in two different CCX (CPU core complexes), the "Zen 5" CCX has 4 cores sharing a 16 MB L3 cache, while the "Zen 5c" CCX shares a 16 MB L3 cache among 8 cores. AMD will probably use a software-based solution to ensure the right kind of workload from the OS is processed by the right kind of CPU core.

A couple of slides from AMD's internal presentation were leaked to the web by Moore's Law is Dead, referencing what's allegedly the next-generation "Zen 5" microarchitecture. Internally, the performance variant of the "Zen 5" core is referred to as "Nirvana," and the CCD chiplet (CPU core die) based on "Nirvana" cores, is codenamed "Eldora." These CCDs will make up either the company's Ryzen "Granite Ridge" desktop processors, or EPYC "Turin" server processors. The cores themselves could also be part of the company's next-generation mobile processors, as part of heterogenous CCXs (CPU core complex), next to "Zen 5c" low-power cores.

In broad strokes, AMD describes "Zen 5" as introducing a 10% to 15% IPC increase over the current "Zen 4." The core will feature a larger 48 KB L1D cache, compared to the current 32 KB. As for the core itself, it features an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage gets 6 ALUs, compared to the current 4. The floating point unit gets FP-512 capabilities. Perhaps the biggest announcement is that AMD has increased the maximum cores per CCX from 8 to 16. At this point we don't know if it means that "Eldora" CCD will have 16 cores, or whether it means that the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD is leveraging the TSMC 4 nm EUV node for "Eldora," the mobile processor based on "Zen 5" could be based on the more advanced TSMC 3 nm EUV node.

PerformanceDatabases has uncovered details relating to an alleged engineering sample of AMD's Ryzen 8000 "Strix Point" APU—likely insider sourced CPU-Z screengrabs from early last month revealed that the upcoming Zen 5-based laptop chip (in their words): "is built on a 4 nm Process and features the Big.Little CPU architecture with 4 Performance Cores and 8 Efficiency Cores. Both the P and E-Cores support hyper-threading. On the P-Core and E-Core, the L1 Data cache is 48 KB, while the L1 instruction cache is 32 KB. Each P Core boasts 1 MB of cache, and with E-Cores, it looks like there are 4 in a group, sharing 1 MB of L2 Cache. This setup is quite similar to Intel's design. Keep in mind, it's still in the engineering sample (ES) stage, so there's more to come. We'll keep you posted on any further updates!"

Another "AMD Strix - Internal GPU" example emerged late last week, this time in the form of a leaked HWInfo64 screen grab with some information completely covered up—the visible parts seems to point to this "Strix Point" APU featuring a core configuration as seen in the earlier leak, along with 1024 unified shaders. We can presume that the sampled Zen 5-based mobile APU possessing 16 RDNA 3.5 compute units (16 × 64 = 1024). Other details include a 45 W TDP rating, and the socket type being FP8 (as utilized by current Ryzen 7040U and 7040H(S) mobile SoCs). The 512 MB GDDR6 memory configuration is very likely an error—according to HWInfo64, the tested system was fitted with 32 GB of LPDDR5 memory. "Strix Point" looks to be the logical successor (in 2024) to AMD's current "Phoenix" lineup of mobile processors, as featured in gaming handhelds and laptops. PC hardware enthusiasts are expressing excitement about the upcoming APU series wielding impressive iGPU performance, with the potential to rival modern discrete mobile solutions.

AMD is aiming to launch its Ryzen 8000 desktop CPUs, codenamed "Granite Ridge," at some point next year. The next generation Zen 5 core microarchitecture is expected to arrive alongside (Navi) RDNA 3.5 iGPU cores according to the last batch of Team Red product roadmaps. Today, hardware tipsters Olrak29_ and Kepler_L2 have made claims on social media that part of the Ryzen 7000 CPU legacy will continue with the succeeding desktop processor lineup—we already know that Granite Ridge will exist as a Socket AM5 package, but today's leak proposes that these next-gen chips are lined up to utilize the same IO die as sported by AMD's current Zen 4 desktop family.

These new rumors suggest that the "reused" Ryzen 7000 IOD (I/O Die) chiplet will grant the familiar allocation of 28 PCIe Gen 5 lanes, memory controllers, USB functions, plus RDNA 2 iGPU cores. Wccftech points out that: "...interestingly, AMD lists the Ryzen 7000 "desktop" CPUs with Navi 3.0 support whereas the Radeon 710M iGPU in fact is based on the RDNA 2 graphics core. The next-gen lineup was mentioned to support the newest RDNA 3.5 GPU core which will be coming to the Strix APU family next year but that isn't the case either." The article proposes that "RDNA 3.5 GPU cores on the AM5 platform" could arrive with the advent of upcoming Ryzen APUs—namely 6 nm Rembrandt (6000G) and 4 nm Phoenix (7000G) desktop solutions.

Beating previous reports that AMD is increasing the CPU core count of its mobile monolithic processors from the present 8-core/16-thread to 12-core/24-thread; we are learning that the next-gen processor from the company, codenamed "Strix Point," will in fact be the company's first hybrid processor. The chip is expected to feature two kinds of CPU cores, with "Zen 5" being the microarchitecture behind the performance cores, and "Zen 5c" behind the efficiency cores. An engineering sample featuring 4 P-cores, and 8 E-cores, surfaced on the web, thanks to Performancedatabases. A HWiNFO screenshot reveals the engineering sample's core-configuration of 4x P-cores and 8x E-cores, with identical L1 cache sizes. Things get a little fuzzy with the L2 cache size detection, and L3 cache.

We know from the current "Zen 4c" core design that it is essentially a compacted version of "Zen 4" designed for higher-density chiplets that have 16 cores; and that it has both the same ISA and IPC as "Zen 4," with the only difference being that "Zen 4c" is designed with lower amounts of shared L3 caches at their disposal, are generally configured with lower clock speeds, and have higher energy efficiency than "Zen 4." "Zen 4c" cores also 35% smaller in die-area than "Zen 4." The company could develop "Zen 5c" CPU cores with similar design goals.

AMD is preparing its Ryzen 5 7500F processor for a global launch according to reports from earlier today—Team Red's German operation has since informed local media outlets about its updated international release strategy for the iGPU-less Zen 4 desktop SKU. Markus Lindner, a regional company spokesman stated: "This processor model will be available starting July 23, 2023 at 9PM ET. It will be available in greater China as a processor-in-box, and in the rest of world as an option for select system builders."

Chinese reviewers have been getting hands-on experience with the Ryzen 5 7500F, with early reports pointing to impressive performance for its price point ($180) when lined up against competing Intel Core i5-13400 and i5-13400F CPUs. International buyers could express concern regarding AMD Germany's mentioning that availability will be somewhat limited to system integrators. Hopefully these "select system builders" will have good distribution links to retail outlets—70% of TPU quick poll participants expressed interest in seeing a western launch (prior to AMD's "global" announcement).

Phoronix has recently uncovered an intriguing Linux update, with kernel improvements being prepared to handle greater microcode payloads—they believe that "future AMD CPUs will be getting larger microcode patches." The timing could suggest that upcoming Zen 5 processors will be likely candidates to meet new requirements: "Right now the Linux kernel has a maximum microcode patch size for AMD CPUs that is three times the kernel's page size (typically 4K). But with a patch (published on July 20) that will "increase substantially" to eight times the page size. The increase is intentionally quite a magnitude larger in order to avoid future patches further having to bump the patch size limit in later generations." Earlier this month, some GitHub entries demonstrated that AMD engineers had patched Linux 6.5 with updates for "Family 26" (1Ah) CPU enablement," which Phoronix believes to be for next-gen platforms (Zen 5): "It's also not elaborated on why the CPU microcode size will be increasing. In any event the simple patch to bump the AMD CPU microcode limit is now out for review. It's also marked for back-porting to existing stable kernel versions."

It looks like the monolithic silicon that succeeds "Phoenix," codenamed "Strix Point," will finally introduce an increase in CPU core counts for the thin-and-light and ultraportable mobile platforms. "Strix Point" is codename for the next-generation APU die being developed at AMD, which, according to a leaked MilkyWay@Home benchmark result, comes with a 12-core/24-thread CPU.

The silicon is identified by MilkyWay@Home with the OPN "AMD Eng Sample: 100-000000994-03_N," and CPU identification string "AuthenticAMD Family 26 Model 32 Stepping 0 -> B20F00." The "Strix Point" CPU could be the second time AMD has increased CPU core-counts per CCX. From "Zen 3" onward, the company increased the cores per CCX from 4 to 8, allowing a single "Zen 3" CCX on the "Cezanne" monolithic silicon to come with 8 cores. It's highly likely that with "Zen 5," the company is increasing the cores/CCX to 12, and that "Strix Point" has one of these CCXs.

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According to the Linux Kernel Mailing List, AMD started to enable next-generation processors by submitting patches to the Linux kernel. Codenamed Family 1Ah or Family 26 in decimal notation, the set of patches corresponds to the upcoming AMD Zen 5 core, which is the backbone of the upcoming Ryzen 8000 series processors. The patches have a few interesting notes, namely few of them being: added support for the amd64_edac (Error Detection and Correction) module and temperature monitoring; added PCI IDs for these models covering 00h-1Fh and 20h; added required support in k10temp driver.

The AMD EDAC driver also points out that the Zen 5 server CPUs will max out with 12-channel memory. Codenames 0-31 correspond to next-generation EPYC, while 40 to 79 are desktop and laptop SKUS. Interestingly, these patches are just the start, as adding PCI IDs and temperature drivers are basic enablement. With the 2024 launch date nearing, we expect to see more Linux kernel enablement efforts, especially with more complicated parts of the kernel.

AMD made its upcoming Ryzen 8000 CPU series official earlier this week during a "Meet the Experts" presentation - a roadmap demonstrates that this next-generation "Zen 5" + "Navi 3.5" mainstream desktop processor lineup is expected to arrive in 2024. Leaked information (from last month) points to "Granite Ridge" being AMD's codename for the upcoming processor product range, with high-end examples maxing out at 16 CPU cores across two CCDs. Benchleaks has recently spotted a pair of curious looking AMD engineering samples - entries have appeared on the einstein@home and LHC@home distributed computing platforms.

The mystery SKU seems to be a prototype CPU model that sports 8 cores and 16 threads - the AMD product number (OPN) for this unit is "00-000001290-11_N" which does not correspond to anything currently on the market. A Family ID of 26 is specified - Benchleaks theorizes that this number assignment is "Zen 5" specific - given that the existing Family 25 (19H) identifier was assigned to Zen 3 and 4. It should be noted that one of AMD's alleged test systems appears to have been running unreleased graphics hardware - a non-specific Radeon unit (with 12 GB of VRAM) is mentioned within einstein@home's information dump, this could be a potential mid-range RX 7000-series card. A Radeon RX 7900 GRE GPU with an unusually low video memory allocation of 16 GB is listed in LHC@home's entry.

AMD in one of its Meet the Experts presentations to the retail channel vendors, confirmed that the next-generation "Zen 5" architecture will see its desktop part branded under the Ryzen 8000 series. The company has known to skip a thousand-number sequence each generation for its mainstream-desktop series, the way it skipped Ryzen 4000 series nomenclature between the "Zen 2" based Ryzen 3000 "Vermeer" and "Zen 3" based Ryzen 5000 Vermeer; and more recently, between "Vermeer" and the "Zen 4" based Ryzen 7000 "Raphael," which makes this an interesting development. AMD's next-generation mainstream-desktop processor is expected to be codenamed "Granite Ridge," it will feature up to 16 "Zen 5" CPU cores across up to two CCDs. The processor I/O (and its 6 nm cIOD) is expected to be largely carried over, except that it could be upgraded with support for higher DDR5 memory speeds.

Another major disclosure is the very first mention of "Navi 3.5" This implies an incremental to the "Navi 3.0" generation (Radeon RX 7000 series, RDNA3 graphics architecture), which could even be a series-wide die-shrink to a new foundry node such as TSMC 4 nm, or even 3 nm; which scoops up headroom to dial up clock speeds. AMD probably finds its current GPU product stack in a bit of a mess. While the "Navi 31" is able to compete with NVIDIA's high-end SKUs such as the RTX 4080, and the the company expected to release slightly faster RX 7950 series to have a shot at the RTX 4090; the company's performance-segment, and mid-range GPUs may have wildly missed their performance targets to prove competitive against NVIDIA's AD104-based RTX 4070 series, and AD106-based RTX 4060 series; with its recently announced RX 7600 being based on older 6 nm foundry tech, and performing a segment lower than the RTX 4060 Ti.

AMD's next-generation Ryzen 8000 "Granite Ridge" desktop processor based on the "Zen 5" microarchitecture, will continue to top out at 16-core/32-thread as the maximum CPU core-count possible, says a report by PC Games Hardware. The processor will retain the chiplet design of the current Ryzen 7000 "Raphael" processor, with two 8-core "Zen 5" CCDs, and one I/O die. It's very likely that AMD will reuse the same 6 nm client I/O die (cIOD) as "Raphael," just the way it used the same 12 nm cIOD between Ryzen 3000 "Matisse" and Ryzen 5000 "Vermeer;" but with updates that could enable higher DDR5 memory speeds. Each of the up to two "Eldora" Zen 5 CCDs has 8 CPU cores, with 1 MB of dedicated L2 cache per core, and 32 MB of shared L3 cache. The CCDs are very likely to be built on the TSMC 3 nm EUV silicon fabrication process.

Perhaps the most interesting aspect of the PCGH leak would have to be the TDP numbers being mentioned, which continue to show higher-performance SKUs with 170 W TDP, and lower tiers with 65 W TDP. With its CPU core-counts not seeing increases, AMD would bank on not just the generational IPC increase of its "Zen 5" cores, but also max out performance within the power envelope of the new node, by dialing up clock speeds. AMD could ride out 2023 with its Ryzen 7000 "Zen 4" processors on the desktop platform, with "Granite Ridge" slated to enter production only by Q1-2024. The company could update its product stack in the meantime, perhaps even bring the 4 nm "Phoenix" monolithic APU silicon to the Socket AM5 desktop platform. Ryzen 8000 is expected to retain full compatibility with existing Socket AM5, and AMD 600-series chipset motherboards.

DigiTimes has been informed that many of TSMC's customers are likely to postpone usage of the foundry's 3 nm process node into 2024 or beyond, due to a slowdown in the PC hardware market - insider sources suggest that AMD will be sticking with 4 nm and 6 nm nodes for many of its future CPU lineups. The next generation Zen 5-based family is expected to launch in 2024 - which aligns with information issued by AMD via financial reports - a roadmap (based on DigiTime's findings) points to AMD offering a range of mainstream desktop (Granite Ridge) and laptop/mobile CPUs (Fire Range).

No high-end desktop (HEDT) options are marked for release in 2024, and DigiTimes reckons that AMD is planning to release Zen 5-based Ryzen Threadripper processors in the following year. The codename for the Ryzen Threadripper 8000-series seems to be "Shimada Peak" and industry experts think that these HEDT CPUs will eventually succeed the Threadripper "Storm Peak" 7000 family (due for launch later in 2023) - a shared socket design is also a likelihood due to AMD wanting to stretch out the lifespan of mounting connection standards by avoiding costly decisions - their sTRX4/SP3r3 socket only survived for one generation.

An AMD engineer inadvertently leaked the core codenames of the company's upcoming "Zen 5" and "Zen 6" microarchitectures. It's important to understand here what has been leaked. "Zen 5" and "Zen 6" are microarchitecture names, just like the current "Zen 4" and past "Zen 3" or older. AMD uses codenames for the CCD (CPU complex dies) based on these microarchitectures, which it shares between Ryzen client and EPYC enterprise processors. For example, the CCD codename for "Zen 3" is "Brekenridge," and for "Zen 4" it is "Durango." AMD also uses codenames for the CPU cores themselves. "Zen 3" CPU cores are codenamed "Cerebrus," and "Zen 4" CPU cores "Persphone." And now, the leak:

The CCD based on the upcoming "Zen 5" microarchitecture is codenamed "Eldora," and the "Zen 5" CPU core itself is codenamed "Nirvana." There's no codename for the CCD based on "Zen 6," but its CPU cores are codenamed "Morpheus." The "Zen 5" microarchitecture will be based on the 3 nm EUV foundry node; while "Zen 6" will be 2 nm EUV. The engineer in the screenshot is contributing to the power-management technology behind "Zen 5" and "Zen 6," and states that their work on "Zen 5" spanned January-December of 2022, which means the development phase of the next "Zen" architecture is probably complete, and the architecture is undergoing testing and refinement. It's also claimed that work on at least the power-management aspect of "Zen 6" has started from January 2023.

Tenstorrent hosted their "Nerds Talking to Nerds About RISC-V" event this week in India where a dozen high profile industry experts hosted technical talks and panels about every facet of the RISC-V landscape and future. Among these are some familiar names to anyone who's been keeping up on the CPU industry; Raja Koduri of his own AI Generative Gaming startup company, Lars Bergstrom of Google, Naveed Sherwani of Rapid Silicon, and of course Jim Keller the CEO of Tenstorrent itself. On the first day of the event a mere 42 minutes into the YouTube live stream during his keynote talk, Jim Keller is providing an overview of Tenstorrent's latest silicon design goals. He presents a slide showing a wide comparison of various competitor's integer performance in SPEC CPU 2017 INT wherein a raw performance value for AMD's yet released "Zen 5" is listed, as well as the operating frequency and TDP of the supposed sample.

The slide shows all of AMD's recent architectures starting with the original "Zen" (Naples) and the improvements each successive generation has made. Also shown is one of Intel's latest "Sapphire Rapids" Xeons, a projected performance point of NVIDIA's in-house CPU architecture "Grace", Amazon's "Graviton" series with a projected result for "Graviton 3," and Tenstorrent's own 8-wide RISC-V architecture as it currently performs in their labs. While all of these are fascinating results in their own right, we're going to narrow in on the "Zen 4" (Genoa) and "Zen 5" results. We can see from the Frequency and TDP charts that "Zen 4" is clocked at 3.8 GHz as it's equal to the Xeon Platinum 8480+ (which itself boosts to 3.8 GHz in light threaded workloads such as this) so is therefore likely a variant of EPYC 9354 or 9454 with its TDP configured at the minimum 240 W. The unnamed "Zen 5" CPU is shown to be running at around 4.0 GHz with the same 240 W TDP, a tiny 5% bump in core clock, while delivering a substantial 30% jump in performance. The most interesting detail here is that nowhere is it listed—as with "Grace" and "Graviton 3"—that this is a projected result.

In no mood to cede its market-share growth to Intel, AMD has reportedly decided to accelerate the development of its next-generation "Zen 5" microarchitecture for debut within 2023. In its mid-2022 presentations, AMD had publicly given "Zen 5" a 2024 release date. This is part of a reading-in-between the lines for a recent GIGABYTE press release announcing server platforms powered by relatively low-cost Ryzen desktop processors. The specific sentence from that release reads "The next generation of AMD Ryzen desktop processors that will come out later this year will also be supported on this AM5 platform, so customers who purchase these servers today have the opportunity to upgrade to the Ryzen 7000 series successor."

While the GIGABYTE press release speaks of a next-generation Ryzen desktop processor, it stands to reason that it is referencing an early release of "Zen 5," and since AMD shares the CPU complex dies (CCDs) between its Ryzen client and EPYC server processors, the company is looking at a two-pronged upgrade to its processor lineup, with its next-generation EPYC "Turin" processor competing with Xeon Scalable "Emerald Rapids," and Ryzen "Granite Ridge" desktop processors taking on Intel's Core "Raptor Lake Refresh" and "Meteor Lake-S" desktop processors. It is rumored that "Zen 5" is being designed for the TSMC 3 nm node, and could see an increase in CPU core count per CCD, up from the present 8. TSMC 3 nm node goes into commercial mass-production in the first half of 2023 as the TSMC N3 node, with a refined N3E node slated for the second half of the year.

AMD in its Ryzen 7000 series launch event shared its near-future CPU architecture roadmap, in which it confirmed that the "Zen 4" microarchitecture, currently on the 5 nm foundry node, will see an optical-shrink to the 4 nm process in the near future. This doesn't necessarily indicate a new-generation CCD (CPU complex die) on 4 nm, it could even be a monolithic mobile SoC on 4 nm, or perhaps even "Zen 4c" (high core-count, low clock-speed, for cloud-compute); but it doesn't rule out the possibility of a 4 nm CCD that the company can use across both its enterprise and client processors.

The last time AMD hyphenated two foundry nodes for a single generation of the "Zen" architecture, was with the original (first-generation) "Zen," which debuted on the 14 nm node, but was optically shrunk and refined on the 12 nm node, with the company designating the evolution as "Zen+." The Ryzen 7000-series desktop processors, as well as the upcoming EPYC "Genoa" server processors, will ship with 5 nm CCDs, with AMD ticking it off in its roadmap. Chronologically placed next to it are "Zen 4" with 3D Vertical Cache (3DV Cache), and the "Zen 4c." The company is planning "Zen 4" with 3DV Cache both for its server- and desktop segments. Further down the roadmap, as we approach 2024, we see the company debut the future "Zen 5" architecture on the same 4 nm node, evolving into 3 nm on certain variants.

AMD in its 2022 Financial Analyst Day presentation announced the codename for the second generation of Ryzen desktop processors for Socket AM5, which is "Granite Ridge." A successor to the Ryzen 7000 "Raphael," the next-generation "Granite Ridge" processor will incorporate the "Zen 5" CPU microarchitecture, with its CPU complex dies (CCDs) built on the 4 nm silicon fabrication node. "Zen 5" will feature several core-level designs as detailed in our older article, including a redesigned front-end with greater parallelism, which should indicate a much large execution stage. The architecture could also incorporate AI/ML performance enhancements as AMD taps into Xilinx IP to add more fixed-function hardware backing the AI/ML capabilities of its processors.

The "Zen 5" microarchitecture makes its client debut with Ryzen "Granite Ridge," and server debut with EPYC "Turin." It's being speculated that AMD could give "Turin" a round of CPU core-count increases, while retaining the same SP5 infrastructure; which means we could see either smaller CCDs, or higher core-count per CCD with "Zen 5." Much like "Raphael," the next-gen "Granite Ridge" will be a series of high core-count desktop processors that will feature a functional iGPU that's good enough for desktop/productivity, though not gaming. AMD confirmed that it doesn't see "Raphael" as an APU, and that its definition of an "APU" is a processor with a large iGPU that's capable of gaming. The company's next such APU will be "Phoenix Point."

AMD in its recent interview with TechPowerUp had asserted that 3D Vertical Cache (or 3DV Cache), isn't a one-off technology and that it would be a continual part of its roadmap. In its 2022 Financial Analyst Day presentation, the company confirmed this, by announcing variants of its CPU chiplets that have 3DV Cache, extending to both the upcoming "Zen 4" microarchitecture, and the upcoming "Zen 5," which it unveiled today.

EPYC "Genoa" is codename for the upcoming line of server processors based on the "Zen 4" CPU microarchitecture, with CPU core-counts of up to 96-core/192-thread. These feature the standard "Zen 4" CCD. The company hasn't yet announced the last-level cache (L3 cache) size of the standard "Zen 4" CCD. The company will launch the EPYC "Genoa-X" processor, which much like the EPYC "Milan-X," will incorporate 3DV Cache, with a stacked L3 cache die on top of the chiplet. "Genoa-X" is slated for a 2023 debut.

AMD in its Financial Analyst Day 2022 presentation, unveiled its next-generation "Zen 5" CPU microarchitecture. The company's latest CPU microarchitecture roadmap also confirms that variants of its "Zen 4" CCDs with 3D Vertical Cache (3DV Cache) are very much in the works, and there will be variants of the EPYC "Genoa" processors with 3DV Cache, besides standard ones.

AMD stated that it completed the design goal of the current "Zen 3" architecture, by building it on both 7 nm and 6 nm nodes (the latter being the client "Rembrandt" processor). The new "Zen 4" architecture will debut on the 5 nm node (TSMC N5), and could see a similar optical shrink to the newer 4 nm node somewhere down the line, although AMD wouldn't specify whether it's on the enterprise segment, or client. The next-gen "Zen 5" architecture will debut on 4 nm, and see an optical shrink to 3 nm on some future product.