During your commute, do you find yourself grabbing the subway handle, half-awake, or idly gazing at the roadside shops? Perhaps you pass the time scrolling on your phone until you reach your destination station. Whether it's a 15-minute bus ride or a half-hour subway journey, commuting often feels like a less-than-ideal use of time. However, with all these minutes adding up, the time spent is significant. How to make the tedious journey productive? BOOX Palma has the solution.

Petite & Light: Bustling Commutes, Easy Moves
When a time-killer is needed on the go, some people opt for a book. However, flipping through a book becomes a real challenge in a packed carriage with no available seats, and people constantly getting on and off. Not to mention, sometimes you need a free hand to grab onto something for balance. An e-reader may be a better choice. But navigating a typical tablet-sized e-reader with your thumb is not always convenient, and holding it for an extended period may strain your wrist. To deal with all these inconveniences, BOOX Palma is here to help. The petite gadget is the smallest in the BOOX lineup. As its name suggests, this 6.13" mobile ePaper fits your palm, weighing just half as much as a common paperback book. Running on an Android system, it offers a familiar user experience with quick tapping and swiping. During multiple transfers, you can easily slip it in and out of your pocket—no more disruptions to your pace in the urban bustle.

Apple has been experimenting with Large Language Models (LLMs) that power most of today's AI applications. The company wants these LLMs to serve the users best and deliver them efficiently, which is a difficult task as they require a lot of resources, including compute and memory. Traditionally, LLMs have required AI accelerators in combination with large DRAM capacity to store model weights. However, Apple has published a paper that aims to bring LLMs to devices with limited memory capacity. By storing LLMs on NAND flash memory (regular storage), the method involves constructing an inference cost model that harmonizes with the flash memory behavior, guiding optimization in two critical areas: reducing the volume of data transferred from flash and reading data in larger, more contiguous chunks. Instead of storing the model weights on DRAM, Apple wants to utilize flash memory to store weights and only pull them on-demand to DRAM once it is needed.

Two principal techniques are introduced within this flash memory-informed framework: "windowing" and "row-column bundling." These methods collectively enable running models up to twice the size of the available DRAM, with a 4-5x and 20-25x increase in inference speed compared to native loading approaches on CPU and GPU, respectively. Integrating sparsity awareness, context-adaptive loading, and a hardware-oriented design pave the way for practical inference of LLMs on devices with limited memory, such as SoCs with 8/16/32 GB of available DRAM. Especially with DRAM prices outweighing NAND Flash, setups such as smartphone configurations could easily store and inference LLMs with multi-billion parameters, even if the DRAM available isn't sufficient. For a more technical deep dive, read the paper on arXiv here.

Today, Brother International Corporation introduced its newest inkjet printer model, the MFC-J1800DW Print & Cut All-in-One Color Inkjet Printer, the brand's first printer to feature automatic paper cutting capabilities. Print & Cut utilizes innovative Brother Blade Sensor Technology (BST) designed to cut full letter pages in half with precision. For home, small business or crafting, the Print & Cut features full print, copy, scan and fax functionality with the added benefit of a paper cutter for cutting perfectly sized cards, invitations, restaurant menus, shipping labels and more.

"Consumers' needs are constantly evolving, and Brother is committed to producing devices that continue to offer the same reliable solutions we're known for, with the latest technology and innovative features," said Alejandra Bello, Product Marketing Manager at Brother International Corporation. "By adding a revolutionary built-in paper cutter to an all-in-one color inkjet printer, we're introducing customers to a new way of printing and cutting."

Realizing the full potential of next-generation deep learning requires highly efficient AI infrastructure. For a computing platform to be scalable and cost efficient, optimizing every layer of the AI stack, from algorithms to hardware, is essential. Advances in narrow-precision AI data formats and associated optimized algorithms have been pivotal to this journey, allowing the industry to transition from traditional 32-bit floating point precision to presently only 8 bits of precision (i.e. OCP FP8).

Narrower formats allow silicon to execute more efficient AI calculations per clock cycle, which accelerates model training and inference times. AI models take up less space, which means they require fewer data fetches from memory, and can run with better performance and efficiency. Additionally, fewer bit transfers reduces data movement over the interconnect, which can enhance application performance or cut network costs.

Momento Note, a leading innovator in the field of digital communication, is thrilled to announce the launch of its groundbreaking product, the Momento Note. This cutting-edge smart note revolutionizes the way we interact with reminders and tasks, taking a timeless tool into the digital era. The yellow sticky note was invented by Dr. Spencer Silver and Art Fry of the esteemed 3M Company in 1980. However, despite advancements in technology, the iconic Post-it Note remained unchanged—until now.

The Momento Note represents a quantum leap in note-taking technology. Leveraging the power of NFC (Near Field Communication), this innovative device transcends the limitations of traditional paper. With the Momento Note, users can store voice recordings, photos, and videos in their reminders, enhancing their organizational capabilities like never before.

Scientists at the Tokyo Institute of Technology have developed a new type of stacked or 3D DRAM that the researchers call Bumpless Build Cube 3D or BBCube 3D, which relies on Through Silicon Vias or TSVs to connect the DRAM dies. This is a different approach to HBM which relies on micro bumps to connect the layers together and the Japanese scientists are saying that their bumpless wafer-on-wafer solution should allow not only for an easier manufacturing process, but more importantly, improved cooling, as the TSVs can channel the heat from the DRAM dies down into whatever substrate the BBCube 3D stack is finally mounted onto.

If that wasn't enough, the researchers believe that BBCube 3D will be able to deliver higher speeds than HBM courtesy of a combination of the TSVs being relatively short and "high-density signal parallelism". BBCube 3D is expected to deliver up to a 32 fold increase in bandwidth compared to DDR5 memory and a four fold increase compared to HBM2E memory, while at the same time, drawing less power. The research paper goes into a lot more details for those interested at taking a closer look at this potentially revolutionary shift in DRAM assembly. However, the question that remains unanswered is if this will end up as a real world product some time in the near future, which is all based on how manufacturable BBCube 3D memory will be.

A group of researchers in China have used a new approach to AI to create a full RISC-V processor from scratch. The team set out to answer the question of whether an AI could design an entire processor on its own without human intervention. While AI design tools do already exist and are used for complex circuit design and validation today, they are generally limited in use and scope. The key improvements shown in this approach over traditional or AI assisted logic design are the automated capabilities, as well as its speed. The traditional assistive tools for designing circuits still require many hours of manual programming and validation to design a functional circuit. Even for such a simple processor as the one created by the AI, the team claims the design would have taken 1000x as long to be done by humans. The AI was trained by observing specific inputs and outputs of existing CPU designs, with the paper summarizing the approach as such:

(...) a new AI approach, which generates large-scale Boolean function with almost 100% validation accuracy (e.g., > 99.99999999999% as Intel) from only external input-output examples rather than formal programs written by the human. This approach generates the Boolean function represented by a graph structure called Binary Speculation Diagram (BSD), with a theoretical accuracy lower bound by using the Monte Carlo based expansion, and the distance of Boolean functions is used to tackle the intractability.

Intel has informed customers that it is adjusting the retail packaging for two 13th Generation Raptor Lake processors—the Core i9-13900K and Core i9-13900KS are popular choices for extreme gamers who demand the best from their CPUs, but did the presence of a premium protective shell also attract certain buyers who enjoy displaying silicon-related mantelpieces? Team Blue will be introducing a more sober looking boxed solution for the aforementioned SKUs - effective in universal and Chinese markets. Intel reasons that it wants to save on the volumetric storage of processors during the shipment process—the smaller box designs will result in a unit increase per pallet. By their estimation this redesign could quadruple the number of boxes in each shipping package - from the previous 324 to a new goal of around 1620.

The Core i9-13900K and Core i9-13900KS were shipped (until recently) in "Tier 4" boxes, but Intel's new cost and space saving drive has the two processors destined to sit in their "Tier 2" retail package which appears to be a standard folding paperboard carton (as seen containing Core i7 and lower end SKUs). The announcement included a set of preview renders, but actual boxed dimensions were not shared in the Product Change Notification (PCN) document. The new packaging regime looks smaller when compared to the older combination of a "premium silver tinted plastic wafer package" plus box sleeve. Team Blue will ultimately shave off a few bucks for themselves in the process, but there is no indication that these savings will be passed onto the end user. Tom's Hardware reckons that a late adjustment to retail packaging could foreshadow the arrival of a successor CPU range—Raptor Lake Refresh is speculated to form the next desktop lineup, since the future of Meteor Lake-S is alleged to be in a precarious state.

Samsung has invested heavily in semiconductor manufacturing technology to provide clients with a viable alternative to TSMC and its portfolio of nodes spanning anything from mobile to high-performance computing (HPC) applications. Today, we have information that Samsung will present its SF4X node to the public in this year's VLSI Symposium. Previously known as a 4HPC node, it is designed as a 4 nm-class node with a specialized use case for HPC processors, in contrast to the standard SF4 (4LPP) node that uses 4 nm transistors designed for low-power standards applicable to mobile/laptop space. According to the VLSI Symposium schedule, Samsung is set to present more info about the paper titled "Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells."

As the brief introduction notes, "In this paper, the most upgraded 4nm (SF4X) ensuring HPC application was successfully demonstrated. Key features are (1) Significant performance +10% boosting with Power -23% reduction via advanced SD stress engineering, Transistor level DTCO (T-DTCO) and [middle-of-line] MOL scheme, (2) New HPC options: Ultra-Low-Vt device (ULVT), high speed SRAM and high Vdd operation guarantee with a newly developed MOL scheme. SF4X enhancement has been proved by a product to bring CPU Vmin reduction -60mV / IDDQ -10% variation reduction together with improved SRAM process margin. Moreover, to secure high Vdd operation, Contact-Gate breakdown voltage is improved by >1V without Performance degradation. This SF4X technology provides a tremendous performance benefits for various applications in a wide operation range." While we have no information on the reference for these claims, we suspect it is likely the regular SF4 node. More performance figures and an in-depth look will be available on Thursday, June 15, at Technology Session 16 at the symposium.

We are excited to announce the launch of Poke5, the new member of our 6" eReader lineup. Here you will learn more about the compact eReader with an optimized new design. Poke5 boasts an unparalleled screen-to-body ratio, thanks to its optimized internal construction. Its design prioritizes a refined experience with better grip and viewing comfort. Its 6" touchscreen features E Ink Carta technology with 300 PPI, which mimics the feel of reading on paper and reduces eye fatigue.

Even with the magnetic cover attached, the compact design fits comfortably in the palm of your hand. Additionally, the flush screen design makes the core component of the ePaper screen resistant to impact. The device offers ample storage space for all of your digital content with its upgraded configuration of 2 GB RAM + 32 GB ROM. It also provides expandable storage options through a microSD card or USB-C flash drive. Furthermore, every user can enjoy 10 GB of free cloud storage for Onyx cloud services upon registration.

At VLSI Symposium 2023, scheduled to take place between June 11-16, Intel is set to demonstrate its PowerVia technology working efficiently on an E-Core chip built using the Intel 4 node. Conventional chips have power and signal interconnects distributed across multiple metal layers. PowerVia, on the other hand, dedicates specific layers for power delivery, effectively separating them from the signal routing layers. This approach allows for vertical power delivery through a set of power-specific Through-Silicon Vias (TSVs) or PowerVias, which are essentially vertical connections between the top and bottom surfaces of the chip. By delivering power directly from the backside of the chip, PowerVia reduces power supply noise and resistive losses, optimizing power distribution and improving overall energy efficiency. PowerVia is set to make a debut in 2024 with Intel 20A node.

For VLSI Symposium 2023 talk, the company has prepared a paper that highlights a design made using Intel 4 technology and implements E-Cores only in a test chip. The document states: "PowerVia Technology is a novel innovation to extend Process Scaling by having Power Delivery on the backside. This paper presents the pre and post silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of greater than 90 percent in large areas of the core while showing greater than 5 percent frequency benefit in silicon due reduced IR drop. Successful Post silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristics of the PowerVia testchip is inline with higher power densities expected from logic scaling."

E Ink, the originator, pioneer, and global commercial leader in digital paper technology, today announced that E Ink Gallery 3 has moved into mass production, with customers: Bigme, BOOX, iFlyTek, iReader, PocketBook, Readmoo and AOC expect to launch their products with Gallery 3 with ship dates to customers in 2023 and beyond.

E Ink has been most famous for its line of black and white eReaders available throughout the world, with millions sold each year. Making color available in eReaders has been a focus of the company for several years. With this announcement, the Company's flagship color product will now be found in commercially released products that bring together the benefits of both the color offering, while preserving the low power attributes E Ink is known for. Gallery 3 is suitable for eReader and eNote in digital reading, education and textbooks, professional use and even IoT devices.

E Ink, the originator, pioneer, and global commercial leader in digital paper technology, today announced the launch of E Ink Gallery 3, a next generation of color ePaper for the eReader and eNote markets. E Ink Gallery 3 is based on the E Ink ACeP Advanced Color ePaper platform. In this platform, a full-color gamut is achieved through a four particle ink system: cyan, magenta, yellow and white, which allows a full color gamut at each pixel.

In Gallery 3, the black and white update time has been improved to 350 milliseconds (ms), the fast color mode is 500 ms, standard color mode is 750-1000 ms and best color is achieved at 1500 ms. This is a substantial improvement over the first generation of E Ink Gallery, which had a black and white update time of two seconds and color updates of ten seconds. In addition, Gallery 3 will have an improved resolution of 300 pixels per inch (ppi) versus the earlier 150ppi and an operating temperature of 0-50 degrees Celsius, on par with black and white eReaders.

E Ink, the originator, pioneer, and global commercial leader in digital paper technology, today announced the launch of E Ink Kaleido 3. This new generation of E Ink Kaleido offers richer colors, along with 16 levels of grayscale and 4096 colors, perfect for displaying colorful images and information on eReaders and eNote devices. By optimizing the design of the ePaper module structure, E Ink Kaleido 3 has increased its color saturation by 30 percent compared to the previous generation, E Ink Kaleido Plus. E Ink Kaleido 3 is using E Ink's Print Color ePaper technology, where a color filter array (CFA) is used in conjunction with E Ink's Carta black and white ink film, creating a full color device for a more fully realized eBook shopping and reading experience.

In addition to improved color performance, Kaleido 3 uses E Ink ComfortGaze, a new front light technology designed by E Ink's Front Light Team. ComfortGaze has been engineered to reduce the amount of blue light reflected off the surface of the display, providing further comfort while reading. ComfortGaze has been engineered to reduce the amount of blue light reflected off the surface of the display, providing further comfort while reading with reduced Blue Light Ratio (BLR) and Blue Light Toxicity Factor (BLTF) by up to 60 percent and 24 percent respectively compared to the previous generation of front light design.

AMD processors have been very good at the field of security, on par with its main competitor, Intel. However, from time to time, researchers find new ways of exploiting a security layer and making it vulnerable to all kinds of attacks. Today, we have information that two new research papers are being published at this year's 15th IEEE Workshop on Offensive Technologies (WOOT'21) happening on May 27th. Both papers are impacting AMD processor security, specifically, they show how AMD's Secure Encrypted Virtualization (SEV) is compromised. Researchers from the Technical University of Munich and the University of Lübeck are going to present their papers on CVE-2020-12967 and CVE-2021-26311, respectfully.

While we do not know exact details of these vulnerabilities until papers are presented, we know exactly which processors are affected. As SEV is an enterprise feature, AMD's EPYC lineup is the main target of these two new exploits. AMD says that affected processors are all of the EPYC embedded CPUs and the first, second, and third generation of regular EPYC processors. For third-generation EPYC CPUs, AMD has provided mitigation in SEV-SNP, which can be enabled. For prior generations, the solution is to follow best security practices and try to avoid an exploit.

A new security vulnerability named "Thunderclap" severely compromises security of computers with USB type-C Thunderbolt ports, or machines with Thunderbolt 3 (40 Gbps) ports. This would be pretty much every MacBook released in the past two years, Macs, and PCs with certain aftermarket Thunderbolt 3 adapters. Chronicled in a paper by the Department of Computer Science and Technology at the University of Cambridge, Rice University and SRI International, is a method for Thunderbolt devices to bypass the host machine's IOMMU (I/O memory management unit), and read its main memory over DMA.

An IOMMU translates address-spaces between devices and main memory, and hence protects your memory's contents being read by just about any device. The group has detailed possible ways to mitigate this vulnerability, and forwarded these mitigations to Apple, Intel, and Microsoft. For now no public mitigation exists other than disabling the Thunderbolt controller of your machine in your motherboard's UEFI setup program.

This piece of news is slightly off the beaten path for our usual coverage of solely PC hardware or gaming, but I think that Samsung's overall size in the worldwide market merits a headline. Sustainability efforts have been increasing for a number of years now (albeit slower than many of us would like), and Samsung, being the giant corporation that it is with threads in all sorts of product lines, has taken a bold step in achieving environmental sustainability. Plastic used for product packaging is being phased out with recyclable, environmentally-friendly products. Some plastic usages will be kept, though even those will see a revised, recycled-plastic or bioplastic materials.