Report an Error

ADATA Legend 850 1 TB (SM2269XT + YMTC CDT1B)

1 TB
Capacity
SM2269XT
Controller
TLC
Flash
PCIe 4.0 x4
Interface
M.2 2280
Form Factor

Multiple hardware versions found.

Performance could vary due to unannounced flash/controller changes.

Front
SSD Controller
Controller
NAND Die
NAND Die
The ADATA Legend 850 is a solid-state drive in the M.2 2280 form factor, launched in 2023. It is only available in the 1 TB capacity listed on this page. With the rest of the system, the ADATA Legend 850 interfaces using a PCI-Express 4.0 x4 connection. The SSD controller is the SM2269XT from Silicon Motion, a DRAM cache is not available. ADATA has installed 128-layer TLC NAND flash on the Legend 850, the flash chips are made by YMTC. Please note that this SSD is sold in multiple variants with different NAND flash or controller, which could affect performance, the "Notes" section at the end of this page has more info. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are processed more quickly. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The Legend 850 is rated for sequential read speeds of up to 5,000 MB/s and 4,500 MB/s write; random IOPS reach up to 400K for reads and 550K for writes.
At its launch, the SSD was priced at 80 USD. The warranty length is set to four yearsADATA guarantees an endurance rating of 1000 TBW, a good value.

Solid-State-Drive

Capacity: 1 TB (1024 GB)
Hardware Versions:
Overprovisioning: 70.3 GB / 7.4 %
Production: Active
Released: 2023
Price at Launch: 80 USD
Part Number: ALEG-850-1TCS
Market: Consumer

Physical

Form Factor: M.2 2280 (Single-Sided)
Interface: PCIe 4.0 x4
Protocol: NVMe 1.4
Power Draw: Unknown

Controller

Manufacturer: Silicon Motion
Name: SM2269XT
Architecture: ARM 32-bit Cortex-R8
Core Count: Dual-Core
Frequency: 650 MHz
Foundry: TSMC
Process: 12 nm
Flash Channels: 4 @ 1,600 MT/s
Chip Enables: 8
Controller Features: HMB (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT1B)
Rebranded: (Rebranded by ADATA)
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: 2 chips @ 4 Tbit
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Dies per Chip: 8 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 20 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)		 3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: None
Host-Memory-Buffer (HMB): 64 MB

Performance

Sequential Read: 5,000 MB/s
Sequential Write: 4,500 MB/s
Random Read: 400,000 IOPS
Random Write: 550,000 IOPS
Endurance: 1000 TBW
Warranty: 4 Years
MTBF: 2.0 Million Hours
Drive Writes Per Day (DWPD): 0.7
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • AES-256
RGB Lighting: No
PS5 Compatible: Yes

Notes

Controller:

The difference between this and the non-XT revision is that this revision doesn't support DRAM, in fact it supports HMB (Host Memory Buffer). Also, this revision has a different package (247-balls FCCSP).

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side
Jun 1st, 2024 13:38 EDT change timezone

Latest GPU Drivers

New Forum Posts

Popular Reviews

Controversial News Posts