AMD Readies New Southbridge Chipset with Native USB 3.0 Support

[btarunr]

Although USB 3.0 and SATA 6 Gb/s served as features central to new motherboard models by manufacturers for an entire year, their adoption by chipset vendors has been rather slow. While AMD has integrated SATA 6 Gb/s into its SB850 southbridge, which features a 6-port SATA 6 Gb/s RAID controller, neither Intel nor AMD have USB 3.0 integrated, with no real indication Intel doing so in the foreseeable future. Sources in the motherboard industry, however, reveal that AMD is designing a new southbridge that integrates a USB 3.0 controller, just like present chipsets have USB 2.0.

AMD's move follows a recent announcement of collaboration with Renesas, the company behind the popular NEC uPD720200 controller, to promote USB 3.0 as an industry standard, and a new universal UASP driver model for USB 3.0 controllers. The new southbridge is codenamed "Hudson D1", which will release along with AMD's 40 nm Ontario Fusion APUs in Q4-2010. The company also plans to release the Llano Fusion APU in 2011.

View at TechPowerUp Main Site

 

[mdsx1950]

Nice to see that USB 3.0 is slowly getting popular now.

 

[inferKNOX]

Very nice. I did have a feeling there was a reason for the A in 890FXA-GD70 and GA-890FXA-UD7.
Maybe this will be a B?
I think AMD might make another revision to the NB (& maybe SB while they're at it) when PCIe 3.0 is ratified too.

 

[Mussels]

good to see it integrated, not a huge difference really, we just get a few more 3.0 ports on newer boards.

 

[TheLostSwede]

Why would you get more ports?
If they're implementing the Renesas controller you'll still only get two ports.
Renesas is working on a four port host controller, so it's possible AMD will go for that design.
Considering how much bandwidth full USB 3.0 speed takes up, I doubt we'll go beyond four ports until PCI Express 3.0 comes out.
At least AMD has Hypertransport, unlike Intel's antiquated DMI bus which the company just doesn't seem to be able to retire, so there should be any bandwidth issues on the bus, like you get with most Intel chipsets.

 

[robal]

Nice.

Q4-2010 ?
That would mean that AMD will be way ahead of Intel in this regard.

Very good. I was looking forward to seeing mobos with all native USB 3.0 ports, not a mix of SB 2.0 and discrete 3.0

 

[btarunr]

Why would you get more ports?
If they're implementing the Renesas controller you'll still only get two ports.

Nah, in a southbridge, normally USB 2.0 is deployed as two hubs of 6 or 4 ports. AMD is integrating USB 3.0 to that scale.

At least AMD has Hypertransport, unlike Intel's antiquated DMI bus which the company just doesn't seem to be able to retire, so there should be any bandwidth issues on the bus, like you get with most Intel chipsets.

Partly incorrect. AMD uses ALink III as the chipset bus on 8-series chipsets. ALink III is physically PCI-Express 2.0 x4, while Intel's DMI is PCI-Express 1.1 x4 with a proprietary data protocol. DMI has a puny bandwidth of 1 GB/s per direction (if you add protocol overhead the actual bandwidth is lower), while for ALink III it's theoretically double (2 GB/s per direction). Until 8-series AMD's ALink I/II were PCI-Express 1.1 links with similar bandwidths as DMI.

The only chipset maker that used HyperTransport as a chipset bus is NVIDIA. It used a HyperTransport 1.0 8-bit link between the SPP and MCP with a massive bandwidth of 8 GB/s or 4 GB/s per direction, and that they did back in 2006.

NVIDIA needed the kind of bandwidth HyperTransport have because the PCI-Express resources were split up between the SPP and MCP in older versions of nForce (like nForce 4, 5 series, and 6 series). So each chip gave out a PCI-Express 1.1 x16 port for graphics cards in 2-way SLI.

 

[Mussels]

Why would you get more ports?
If they're implementing the Renesas controller you'll still only get two ports.
Renesas is working on a four port host controller, so it's possible AMD will go for that design.
Considering how much bandwidth full USB 3.0 speed takes up, I doubt we'll go beyond four ports until PCI Express 3.0 comes out.
At least AMD has Hypertransport, unlike Intel's antiquated DMI bus which the company just doesn't seem to be able to retire, so there should be any bandwidth issues on the bus, like you get with most Intel chipsets.

because when its built into the NB/SB, they dont have to worry about external PCI-E lanes running out of bandwidth. existing USB 2.0 ports will be replaced with 3.0 ports - meaning they could theoretically give us 10x USB 3.0 ports to replace the 10x USB2.0 ports we already get on high end boards.

 

[HillBeast]

So I'm guessing we won't see this in computers until Fusion. Not really that big of an accomplishment for AMD IMHO. Sure it's good that it will have USB 3.0 but I'm pretty sure Intel said they will have USB 3.0 and SATA3 on Sandy Bridge natively, so really it's not that big of a deal.

 

[mascotzel]

not that soon
http://www.google.com/search?hl=en&...1&aqi=g4g-c2g2&aql=&oq=intel+usb+3.0&gs_rfai=

 

[TheLostSwede]

It's really not that easy, USB 3.0 has a lot more limitations that USB 2.0 in terms of motherboard trace lengths etc, so no, you won't be seeing a ton of ports on the boards and USB 3.0 won't be replacing all of the USB 2.0 ports in a chipset implementation.

On top of that, if you're going to be able to provide full bandwidth to each of the USB 3.0 ports, then you need to have the same bandwidth available from the chipset to the CPU or you're going to run into some serious problems. It's not a matter of external PCI Express lanes running out of bandwidth, as there's no such issue, it's a matter of there being enough bandwidth from the southbridge to the CPU in the case of AMD's chipsets. AMD has not suffered from poor PCI Express bandwidth like Intel, so that's a non issue in this case.

And no, Intel will NOT have integrated USB 3.0 support at all in 2011 and only a pair of SATA 6Gbps ports on top of that, with some chipsets only featuring a single port.

 

[btarunr]

On top of that, if you're going to be able to provide full bandwidth to each of the USB 3.0 ports, then you need to have the same bandwidth available from the chipset to the CPU or you're going to run into some serious problems.

Not true. A USB controller shares bandwidth between all ports of a hub. So even bandwidth sufficient for two ports (2 x 480 MB/s) is sufficient to run an 8-port setup.

Besides, when AMD is able to manage its bandwidth budget to accommodate a 6-port SATA 6 Gb/s controller (which is actually more bandwidth intensive since bandwidth isn't shared between ATA channels), then it can accommodate a USB 3.0 controller.

Maybe there will be one 2-port USB 2.0 controller integrated into the southbridge (just like SB850 packs one 2-port USB 1.1 controller) to leave at least two ports for the front-panel (since most PC cases have front-panel/header designed for USB 1.1/2.0, and that USB 3.0 has a different front-panel header layout).

 

[TheLostSwede]

Right, so you want crippled performance then? FYI there are NO USB 3.0 implementations that work that way today and obviously as AMD is licensing a design from Renesas, it's unlikely that they'll be able to do too many changes to it. What would be the point of having a bunch of ports if you could only use them at 10% of their full speed? Then you might as well just stick a single port controller and a USB 3.0 hub inside the chipset as it'd give you the same functionality. You really need to read up a bit more on USB 3.0, as you're obviously not following the developments very closely.

 

[btarunr]

Right, so you want crippled performance then?

Huh? That's how USB works. It's not that every USB 2.0 port in your system can give its full 480 Mbps bandwidth at the same time. Your southbridge-embedded controller distributes bandwidth among two or three hubs, each distributes 480 Mbps among ports, leaving you 8~12 ports on your motherboard. That's how USB's port hierarchy is.

So a USB 3.0 embedded southbridge controller will at most need 960 or 1440 MB/s of bandwidth. ALink III has 4096 MB/s, so it's very much within the bandwidth budget, and can coexist with that meaty 6-port SATA 6 Gb/s AHCI/RAID controller.

 

[TheLostSwede]

No, that's how USB used to work, you see, there are two kinds of USB host controllers, UHCI/OHCI and EHCI of which the latter offer full bandwidth to pair of ports and this is how USB 3.0 is designed. With UHCI the bandwidth is shared between all ports in the system, which is a crappy solution. AMD's 800-series of southbridges features no less than three EHCI controllers which allows for six ports of near enough full speed bandwidth. USB 3.0 also uses EHCI as otherwise you'd get crap performance. So no, it's not how USB works any more.

This is also the standard that Intel controls, also referred to as xHCI and this is what Intel doesn't want to move from revision 0.9x to 1.0 as then Intel would have to implement USB 3.0 into its chipsets.

As such you need a lot more bandwidth available per pair of USB 3.0 ports than you claim, in fact, each EHCI pair requires the full 5Gbps worth of bandwidth. This is also why it's so hard to implement USB 3.0, not counting the physical board implementation, as a single lane of PCI Express gen 1 bandwidth isn't enough. As I said, I very much doubt we'll see more ports, although four shouldn't really be a problem for AMD, especially as Renesas and TI are already working on solutions for this and VIA allegedly has a solution ready...

Forgot to say that USB 3.0 also has much better data routing than USB 2.0, as in it's more like a smart switch than a dumb hub in terms of getting the right bits to the right place as fast as possible.

 

[eidairaman1]

UHCI was the standard Intel used and it was proprietary to Intel.

 

[Mussels]

AMD's 800-series of southbridges features no less than three EHCI controllers which allows for six ports of near enough full speed bandwidth. USB 3.0 also uses EHCI as otherwise you'd get crap performance. So no, it's not how USB works any more.

and my AMD board has 12 ports total. hence, they're splitting the bandwidth exactly as bta said.

 

[ToTTenTranz]

I don't care about southbridges.

I want single-bridge designs with an updated IGP!

 

[WarEagleAU]

Would be nice to have 6 to 10 back mounted USB 3.0 ports and 2 on the front for full 3.0 or 2.0

 

[Imsochobo]

good to see it integrated, not a huge difference really, we just get a few more 3.0 ports on newer boards.

power consumtion is a important thing in a pc.

With more interigated, you get less heat and more power. ofcourse, those parts getting it all interigated gets harder and harder to cool!

but thumbs up for amd here

 

[btarunr]

No, that's how USB used to work, you see, there are two kinds of USB host controllers, UHCI/OHCI and EHCI of which the latter offer full bandwidth to pair of ports and this is how USB 3.0 is designed. With UHCI the bandwidth is shared between all ports in the system, which is a crappy solution. AMD's 800-series of southbridges features no less than three EHCI controllers which allows for six ports of near enough full speed bandwidth. USB 3.0 also uses EHCI as otherwise you'd get crap performance. So no, it's not how USB works any more.

Nope. USB ports in even EHCI (Hi-Speed) is organiesed as SB > Controllers > Root Hubs > Hubs > Ports. The SB gives each controller a PCI or PCI-E connection, the controller gives each root hub that 480 Mbps which it shares among hubs. Each hub has its port. So the actual bandwidth the southbridge would need to set aside for USB would be the cumulative of number of Root Hubs.

In my case (Intel P55 PCH), the PCH is needing to set aside just 192 MB/s in case the USB controllers are populated to the max with bandwidth-intensive devices, not 14 x 48 MB/s. That much is within P55's bandwidth budget.

It's the same way AMD organises its USB 2.0 controllers, and USB 3.0 supports the same standard of port multiplexing USB 2.0 does, which is why companies like VIA (VLI) have been able to come out with multiplex (hub) chips in no time.

http://www.techpowerup.com/111945/VIA_Group_Launches_World_s_First_USB_3.0_Hub_Controller.html

As such you need a lot more bandwidth available per pair of USB 3.0 ports than you claim, in fact, each EHCI pair requires the full 5Gbps worth of bandwidth. This is also why it's so hard to implement USB 3.0, not counting the physical board implementation, as a single lane of PCI Express gen 1 bandwidth isn't enough. As I said, I very much doubt we'll see more ports, although four shouldn't really be a problem for AMD, especially as Renesas and TI are already working on solutions for this and VIA allegedly has a solution ready...

With the port hierarchy model of USB 2.0, like I said AMD will have to allocate 960 or 1440 MB/s for 8 to 12 USB 3.0 ports, and SB8xx southbridge has a PCI-Express 2.0 hub. The SB8xx has a 4 GB/s chipset bus. So it's doable for AMD to have 8~12 USB 3.0 ports.

Forgot to say that USB 3.0 also has much better data routing than USB 2.0, as in it's more like a smart switch than a dumb hub in terms of getting the right bits to the right place as fast as possible.

True, that indicates that with some multiplexing you can reduce the bandwidth requirement of your southbridge controllers.

 

[Mussels]

power consumtion is a important thing in a pc.

With more interigated, you get less heat and more power. ofcourse, those parts getting it all interigated gets harder and harder to cool!

but thumbs up for amd here

what?

you dont get more power at all, and you wont have any extra heat... they're swapping 2.0 ports for 3.0 ports...