Official AMD Radeon 6000 Series Discussion Thread

[Fishymachine]

256 is what we will see.

Yet the die will be big enough for 512bit .More like there will be no Antilles, as even a 1920SP GPU will have 400mm^2(enough for 384bit,even 512 with GDDR3,) and at the very best there will be a Cayman XTX with 1050 core,or dual Barts card(illogical unless AMD makes the Cayman only 50% bigger than Barts)

 

[cheezburger]

Yet the die will be big enough for 512bit .More like there will be no Antilles, as even a 1920SP GPU will have 400mm^2(enough for 384bit,even 512 with GDDR3,) and at the very best there will be a Cayman XTX with 1050 core,or dual Barts card(illogical unless AMD makes the Cayman only 50% bigger than Barts)

1920sp on 32rops? less likely.......why need more shader when you couldn't have brutal force to output the ALU potential? by aceelerating clockrate to achieve the goal? remember PCB board can't substain any clockrate over 1GHZ. like intel's slot 1. graphic card would not be exception! so only way to increase fps is adding rops. not just adding ridiculous shader that exist 32rops can't push it

 

[Fishymachine]

1920sp on 32rops

Actually I said that even a 1920SP SI(Cayman) will have enough die for 384bit(and 48 ROP),and I em fairly sure that the next flagship will be based on a XTX and not a dual GPU.

 

[DriedFrogPills]

one of the rumours was 64 ROPS. So the only thing we can do is settle in for the next 10 days an wait the product announcement is under two weeks away after all, and then all will be revealed
:cool :

 

[tkpenalty]

1920sp on 32rops? less likely.......why need more shader when you couldn't have brutal force to output the ALU potential? by aceelerating clockrate to achieve the goal? remember PCB board can't substain any clockrate over 1GHZ. like intel's slot 1. graphic card would not be exception! so only way to increase fps is adding rops. not just adding ridiculous shader that exist 32rops can't push it

Under your logic GPU manufacturers should OBVIOUSLY put on 128 ROPs, and as many ALU units as possible, but I'm afraid it does not work like that.

The more silicon, the less you get in return; diminishing returns, and this is because when you do pipelineing in a processor's architecture which GPUs extensively use, the latencies will increase; Amdahl's law.

What you do is, either go with higher clock rates, or more efficient processors. The terms ROPS, etc are all just genericisms and you can't compare 'rops' from a HD6k series card to the HD5k card cause the throughput is substantially different.

"remember PCB board can't substain any clockrate over 1GHZ" - what sort of baseless assertion is that?

 

[mastrdrver]

The date of 6770 Barts launch has never slipped.

S/A forum

Ok. Charlie wrote this up a week or so ago. So, once again. For the record. Launch is Oct. 25 +/- a day or so. The PRESS BRIEFING is the 14th. That gives the press a couple of weeks to bench and play with their cards in time to have a story ready for launch. AMD/ATI has done with with their GPU launches the last 3 or more times they've had a new series.

This is business as usual. Anyone says launch is Oct. 12th or 18th they've got the wrong date and cannot tell the difference between a press briefing and a launch.

Next up. The first card out in the series is the 67xx. I don't know specs. Charlie hasn't written that up. However, the 67xx is in Oct. and the 68xx is in Nov. for LAUNCH. Again, this is all available on front page stories of ours.

Now, why is the 67xx launching first? It's not a hard puzzle. wait, hold on, oh I got it ... they need to fill that hole in their lineup. ie a price and performance point to pound the 460 into the ground. Why else bother with that one first?

bueller? bueller? anyone?

if you stick with 256bit bus most likely you will stuck with 48rops...............

Ringbus, what are you talking about? ATI hasn't use a ringbus since R500 and they dropped it because of the inefficiency.

Also you think that the architecture is going to be the same as with R700 and Evergreen which is why 48 Rops doesn't work. Like how nVidia has their GPC (graphic processing cluster), AMD has their version call RPE (render and processing engines):

Beyond 3D post

The ROPs are tied to these. This is how you get 48 for Cayman on a 256 bit bus that we know to be true because of the GPUz shot that even W1zz said he couldn't see it being fake.

 

[LASER]

Gtx 470

after waiting more than 1.5 year i want a card... m not rich but managed to get money for a good future product which i dont need to replace in 1 year...thats y, GTX 275 , 4890 i left those cards and waited for win7 cards... then again for Nvidia but it turned out they are high in everything (price and temp) as compared but now with Gigabytes good cooling and little less price i am planning to buy this card !
28nm by nvidia may take 8 months... i dont know and ATI 6000 is not big deal i guess...as games will be having more details and i want a card which has 8X better tesselation performance...
but i am not pro like u guys so i need some advice..

 

[mastrdrver]

What's another month (for Barts) or two (for Cayman) after 1.5 years?

Even if you get a GTX 470 after these release it can only be better as price should not get worse and maybe a little lower.

No reason to hurry. Wait for the releases and then decide.

 

[inferKNOX]

Wow, to think that AMD has most probably kept tight-lipped about the HD6000s for the past ~5yrs (normal development time of a GPU according to what I've read), and it's the last couple of weeks before release and there's still only tidbits of info on the HDx700 and more-or-less nothing on the HDx800 and HDx900. Even the supposed "leaks" of the Barts details seem to have been deliberate to get people excited and talking.
Guess the strategy they were using to keep Eyefinity secret, that they implemented across the board is working wonders. Impressive (and depressive, if you're like me dying to hear more,) indeed.

 

[Wyverex]

Wow, to think that AMD has most probably kept tight-lipped about the HD6000s for the past ~5yrs (normal development time of a GPU according to what I've read), and it's the last couple of weeks before release and there's still only tidbits of info on the HDx700 and more-or-less nothing on the HDx800 and HDx900. Even the supposed "leaks" of the Barts details seem to have been deliberate to get people excited and talking.
Guess the strategy they were using to keep Eyefinity secret, that they implemented across the board is working wonders. Impressive (and depressive, if you're like me dying to hear more,) indeed.

QFT

Also, anyone else thinking something along these lines:
- 4 simple + 1 complex shader were working wonders for low-intensity scenes and rendered very high FPS (max FPS)
- new 4 medium-complexity-shaders could (more-or-less) keep the same max FPS, yet improve in scenes that require more muscle and get us better minimum and average FPS

 

[dalelaroy]

if you stick with 256bit bus most likely you will stuck with 48rops

if you stick with 48 rops you will have to go 384bit bus

since both amd/nv had stuck with max rop per bus will be impossible to push rop further without more bus. and cayman will not have same number of rops like barts had as it's pointless to add more shader without larger rops operate. so 48 rops has to be 384bit bus. and amd will not go odd config like nvidia and 64 rops cannot put on exist 256bit bus. 32rops on cypress = 8x4 and each rop obtain 32bit bus and that is the minimum limitation that allow ring bus to operate and cannot go below 32bit per rops. which that is the reason why evergreen line was hugely bottleneck that people tend to argue cypress was double of r770 but end up only increase 60%. original r600 are 64bit per rops and r770 are also 64bit/bus until evengreen tweak it to 32bit per rop/bus. it will be impossible to have 64rops on 256bit bus and it will end up each rops only obtain 16bit bus which existed architect won't allow it happen.

however continuing exist 32rops configuration is just pointless because adding shader don't increase frame rate, rops does. also 480 ALU is already the limitation in exist 40nm fabrication and amd won't waste such number of ALU core on only 32rops GPU.... if you know nothing about gpu architecture you better be silence because that will just make you look bad.



then you can't add more rops if you can't have higher bus...exist ringbus architect on both NV/AMD can't allow config like 16bit /rops exist. 32bit/rops is most likely the limitation that ringbus can hold. if amd insist stay on 256bit bus they most likely stuck with 32rops and there for 32rops cause bottleneck to larger number of ALU/shader as frame rate will not increase in largely margin. we all laern from how r770 was bottle neck so much by its rop then why amd want to go on narrow rops/bus if the framerate won't go up in higher number? without higher fillrate shader are pretty much useless.....

256bit bus and you will stuck in 32 rops....



then cayman will stuck at 32 rops....

Cypress has a 256-bit bus and 32 ROPs. 256-bit/32 ROPs = 16-bits per ROP. Are you absolutely sure that it is impossible to have just 16-bits per ROP?

 

[DriedFrogPills]

Cypress has a 256-bit bus and 32 ROPs. 256-bit/32 ROPs = 16-bits per ROP. Are you absolutely sure that it is impossible to have just 16-bits per ROP?

RV700 had a 256bit bus and 16 rops so i think it could more be limited to multiples of 8 rather than x bits pee ROP

 

[Steevo]

1920sp on 32rops? less likely.......why need more shader when you couldn't have brutal force to output the ALU potential? by aceelerating clockrate to achieve the goal? remember PCB board can't substain any clockrate over 1GHZ. like intel's slot 1. graphic card would not be exception! so only way to increase fps is adding rops. not just adding ridiculous shader that exist 32rops can't push it

I sustain over 1Ghz on mine. I can reach 1.1Ghz at 1.35volts, it does require a lower memory clock so it is not beneficial. I'm sure with a voltage hardmod I could reach 1.2 or perhaps a bit higher as the temps are still OK.


ROPS have nothing to do with memory bandwidth.

the ring bus architecture will not allow this happen.

They haven't used ring bus since the X1K series.

 

[cheezburger]

The date of 6770 Barts launch has never slipped.

S/A forum




Ringbus, what are you talking about? ATI hasn't use a ringbus since R500 and they dropped it because of the inefficiency.

Also you think that the architecture is going to be the same as with R700 and Evergreen which is why 48 Rops doesn't work. Like how nVidia has their GPC (graphic processing cluster), AMD has their version call RPE (render and processing engines):

Beyond 3D post
http://img3.imagebanana.com/img/067u3pjw/confidential237549.jpg

The ROPs are tied to these. This is how you get 48 for Cayman on a 256 bit bus that we know to be true because of the GPUz shot that even W1zz said he couldn't see it being fake.

RPE are nothing to do with bus/rop cluster. and amd cant do odd number on 256bit bus. which it hasd been discuss so many time. and your post based on nothing.

I sustain over 1Ghz on mine. I can reach 1.1Ghz at 1.35volts, it does require a lower memory clock so it is not beneficial. I'm sure with a voltage hardmod I could reach 1.2 or perhaps a bit higher as the temps are still OK.


ROPS have nothing to do with memory bandwidth.





They haven't used ring bus since the X1K series.

go read intel blog see how they fail increase clock on their slot 1 cpu....

andropss does matter in bus width on both amd/nv architecture....

 

[wolf]

...go read intel blog see how they fail increase clock on their slot 1 cpu...

were not talking about intel here, only you are, many people can sustain 1000mhz and higher on 5k boards, especially 5850's.

not to mention Nvidia chips have more than one clock domain, the shaders run between 1.3-2ghz.

remember PCB board can't substain any clockrate over 1GHZ

just silly.

 

[cadaveca]

ROPS have nothing to do with memory bandwidth.

ATI's ROPs in Cypress are grouped into 4(which together are called a Render Back End, or RBE), and directly interface with the memory controller. Each of the 4 controllers service 2 RBE's. Although they don't affect bandwidth directly, thier organization will dictate bandwidth by thier needs.


So, you have 4x 64-bit controllers, each service 2x RBE's, which together contain 8 ROPs.

One controller services 8 ROPs.

If we assume that there are 48 ROPs in this new gpu, and ATI keeps the same ROP design(groups of 4), we'd have each controller servicing 3 RBE's(256-bit actually means 4x64-bit, no matter how you slice it, and ergo, each controller would then be servicing 12 ROPs), and this is where the bit about "odd numbers" comes in.

Now, it's more than possible that each RBE contains 6 ROPs, and then 48 ROPs works just fine. However, this would require that Barts and Cayman would be drastically different designs, and this does not fit with AMD's design of 1-2-4 core gpus.

 

[Steevo]

So if they change architecture then they might not be directly related? Or is this a blanket statement that applies to all ATI/AMD cards that have ever been made, and will ever be made?


Slot 1, how long ago was that?

And you do realize that the slot was just a way to change existing CPU sockets, right? So on the board didn't have the silicon made onto it. The reason they never went further was the extra contacts, pins, and total package cost was higher than just a socket made on a board.


Lastly, if a PCB cannot, than how do we arrive at a 2.4Ghz HT, or higher, or memory speeds of 1Ghz, or 2+Ghz DDR?

 

[cadaveca]

So if they change architecture then they might not be directly related? Or is this a blanket statement that applies to all ATI/AMD cards that have ever been made, and will ever be made?

AMD's high end gpus, for some time, now have been basic doubling of the midrange, as this saves money in a variety of ways.

Basically, what it boils down to is a whole other development teams for Cayman and Barts, which is not how they do things, as it's not cost-effective. It would also require a signifigantly different driver-base for the high-end gpu, again requiring more resources. it simply doesn't make for good business.

It's also why many expect Cayman to be a basic doubling of Barts, and ergo, a 512-bit bus and 64 rops, otherwise the architecture on Barts has parts not needed(if cayman is double barts in shaders, but needs less bandwidth and ROPs, then Barts design is flawed), again also because it would be wasting time and resources.

when it comes to the "1ghz" speeds, problems are in the process itself, IMHO, and board design has little to do with that. Current TSMC process just simply requires too much current, or too-high voltage, to be 1ghz spec'd.

In the end, though, because Cayman is a group of three islands, I know that Cayman is 1.5x Barts(or 3x Caicos), and most likely, is 96TMU, 48ROP, on 384-bit bus. I do not expect 512-bit bus, and 64 ROPs, NOT AT ALL.

 

[Steevo]

SOI is the reason we buy a CPU for a few hundred, and a whole graphics cards for a few hundred. Not the PCB.

If they ever move GPU to SOI, they will cost a huge amount, but they performance will be unreal.

 

[cadaveca]

Uh, yeah, that's what I just said, basically. It's the process.

 

[Steevo]

You said it.

So how bout that beer.

 

[largon]

My take:
32RBEs
96TMUs*
480SPUs* (4ALUs/SPU)
256bit ~GDDR5-6400

*divided in three RPEs

 

[cadaveca]

The one thing, largon, is I do not see 256-bit memory feeding 480SPUs, with higher-order shaders.

Maybe if they have lopped of one shader from cypress only, but if they are 4x higher-order, expensive highspeed vram is gooing to be needed.

Although, that make sense as to why we must wait a bit longer for hte high-end SKU..I think high-speed rma is being made right this moment, only.

I don't think 32 ROPs will be enough either. they need that 1/3 boost in memory department to match the shaders, IMHO.

I expect 825mhz clocks(shaders doing more work, generate more heat= reduction of clockspeed; improvements in yields over time on TMSC process account for only small loss.)

 

[mastrdrver]

Ah yes I forgot about the higher speed memory so even they keep the 256 bit bus, with the higher speed memory you get better performance out of the same number of Rops (RBEs).

I know a few wiser than myself on B3D and S/A say that ATI can't do double rops of Barts because there is no way they will be able to keep it under 400mm2.

Also it should be the TMUs that are going to be tied to that new RPE. So 96 could be a possibility if each RPE contained 16 which seems likely to me.

 

[largon]

AMD knows there's positively a boatload of potential in GDDR5's power (= read: frequency) envelope so wider bus is totally unnecessary, bandwidth can be gained more easily by slapping in faster chippery. And I think Cypress' 32RBEs perform perfectly fine, modern games are heavily shader and post processing driven. The only things worth increasing at available silicon area are texturing and shading throughput. And of course AMD needs to fix their broken AF!

And I doubt we'll see a total overhaul in ALU config vs. Cypress. Most likely they just hacked away one simple MADD to increase efficiency of SPUs by showing mercy on the over-booked shader scheduler that seems to plague Cypress. Another scenario I find plausible would be the reduction of two simple MADDs with the addition of one complex MADD. That is, it's either 3+1 or 2+2.