fool and troll are allowed then?
Please explain then what happens when you have L2 cache shared and also L3 shared, compared to an individual core, individual cache.
1: You know better than to double post. You know how to use multi-quote and the edit button.
2: Intel uses a shared L3 cache as well.
3: AMD shared the L2 cache to save space. The benefits out-weight the costs because you won't see a performance loss on a single thread because nothing else is touching the cache.
4: You're being called a fool and troll because you don't know what you're talking about. Not that I condone it and you started by calling me a fan boy, so I wouldn't go opening that can of worms.
5: The main reason is because the IPC is low due to increased chance of branch mis-predictions due to the length of the pipeline as well as how many instructions each "core" (NOT MODULE) can execute per cycle (which Vishera improved to some extent with the improved branch predictor and added x86 decoders.)
Yeah, AMD hasn't gotten it perfect for single-threaded applications, but it's a multi-threaded beast and as soon as AMD improves the IPC a bit more, it will be a lot more powerful than it already is not even considering the benefits to be had once they start producing it on a smaller process.
Also, if you knew anything about how memory heirarchies work, you would know that shared L2 cache would be the bottleneck when both cores in a module are running full power, not on single-threaded applications. So maybe you need to do a bit more research before you start claiming things that have no relevance considering AMD's multi-core performance is pretty good, despite executing fewer IPC.
So all in all, I don't agree with the labeling and I'm guilty of doing it from time to time (I'm trying not to, I really am.
) but there is a reason why people get frustrated and start resorting to such tactics.
All in all, your comments have no factual backing and you're making a boatload of false assumptions... and you know what they say about making assumptions.
We don't need low performance with many cores. We need few cores with high perfomance per core ratio
Or we need to wait for AMD to continue improve how many instructions per clock so all 8 cores run fast. I also don't find many people with Vishera chips complaining about them which usually is a sign that they're not that bad.
4 Modules 2 Cores each you fool
Now now, you don't need to call Prima.Vera a fool, only the pitty is required.