Has there been any news on 16nm yields at TSMC? Last I heard (mid-April) it was said as they looked to be approaching mature levels.
I take that as saying they are able to succeed overall wafer methodologies, multi-patterning flows, and dynamic power density, but not necessarily able to provide any consistency or numbers of decent chips from the process (yield). Knowing the added mask steps (approx. 14 additional) so the understanding is from a wafer start-package-testing, to chip delivery FinFET would take several more weeks. (28nm~2.5mo’s vs. FinFET ~3mo’s).