- Joined
- Oct 9, 2007
- Messages
- 47,231 (7.55/day)
- Location
- Hyderabad, India
| System Name | RBMK-1000 |
|---|---|
| Processor | AMD Ryzen 7 5700G |
| Motherboard | ASUS ROG Strix B450-E Gaming |
| Cooling | DeepCool Gammax L240 V2 |
| Memory | 2x 8GB G.Skill Sniper X |
| Video Card(s) | Palit GeForce RTX 2080 SUPER GameRock |
| Storage | Western Digital Black NVMe 512GB |
| Display(s) | BenQ 1440p 60 Hz 27-inch |
| Case | Corsair Carbide 100R |
| Audio Device(s) | ASUS SupremeFX S1220A |
| Power Supply | Cooler Master MWE Gold 650W |
| Mouse | ASUS ROG Strix Impact |
| Keyboard | Gamdias Hermes E2 |
| Software | Windows 11 Pro |
Intel's 10 nanometer FinFET silicon fabrication is coming together at a slower than expected rate, however when it does, it could vastly enlarge the canvas for the company's chip designers, according to a technical report by Tech Insights. The researchers removed the die of an Intel "Cannon Lake" Core i3-8121U processor inside a Lenovo Ideapad330, and put it under their electron microscope.
Its summary mentions quite a few juicy details of the 10 nm process. The biggest of these is the achievement of a 2.7-times increase in transistor density over the current 14 nm node, enabling Intel to cram up to 100.8 million transistors per square millimeter. A 127 mm² die with nothing but a sea of transistors, could have 12.8 billion transistors. Intel 10 nm node also utilizes third-generation FinFET technology, with a reduction in minimum gate pitch from 70 nm to 54 nm; and minimum metal pitch from 52 nm to 36 nm. 10 nm also sees Intel introduce metallization of cobalt in the bulk and anchor layers of the silicon substrate. Cobalt emerged as a good alternative to tungsten and copper as a contact material between layers, due to its lower resistance at smaller sizes,
View at TechPowerUp Main Site
Its summary mentions quite a few juicy details of the 10 nm process. The biggest of these is the achievement of a 2.7-times increase in transistor density over the current 14 nm node, enabling Intel to cram up to 100.8 million transistors per square millimeter. A 127 mm² die with nothing but a sea of transistors, could have 12.8 billion transistors. Intel 10 nm node also utilizes third-generation FinFET technology, with a reduction in minimum gate pitch from 70 nm to 54 nm; and minimum metal pitch from 52 nm to 36 nm. 10 nm also sees Intel introduce metallization of cobalt in the bulk and anchor layers of the silicon substrate. Cobalt emerged as a good alternative to tungsten and copper as a contact material between layers, due to its lower resistance at smaller sizes,
View at TechPowerUp Main Site
