AMD 3rd Gen Ryzen AM4 Package Capable of Two 8-core Chiplets

[Rahnak]

Su already hinted at parts with more cores after the keynote and if the previous leaks were somewhat right in relation to SKUs... Did Intel's 9900k just get beaten in MT Cinebench by a R5 3600X not running final clocks?

 

[btarunr]

Su already hinted at parts with more cores after the keynote and if the previous leaks were somewhat right in relation to SKUs... Did Intel's 9900k just get beaten in MT Cinebench by a R5 3600X not running final clocks?

I think AMD will come up with a Ryzen 9 extension. Ryzen 7 could be up to 16-thread, and Ryzen 9 up to 32-thread. The chip these guys showed has the MP performance of i9-9900K and market positioning against i7-9700K.

I think the bigger news is that AMD has fully caught up with Intel at IPC.

 

[Xzibit]

In this video you can see the traces for the additional/missing chiplet.

At 1:38-1:45 the light shines on it and is clearly visable.

Gordon goes on to say Lisa Su pretty much confirms they could have more then 8 cores.

 

[Wavetrex]

I love how the cameraman held in position for light to reflect from the "empty spot" showing clearly there's stuff under there.

100% designed for 16 cores on AM4!
Smoking !

Bring it faster AMD, my wallet is itching !

 

[stimpy88]

I'm down for a Ryzen9 16 core CPU! AMD, you did it, you have achieved single core performance parity with Intel. Keep the momentum up, and you will win the market.

It's going to be a long 6 months waiting for this, which will be my first AMD system in 12 years.

Oh, and all nice to see AdoredTV being proved right again, despite all the negativity towards him.

 

[R0H1T]

Interesting tidbit from Toms ~ PCIe 4.0 May Come to all AMD Socket AM4 Motherboards (Updated)
Good guys AMD

 

[Slizzo]

I think AMD will come up with a Ryzen 9 extension. Ryzen 7 could be up to 16-thread, and Ryzen 9 up to 32-thread. The chip these guys showed has the MP performance of i9-9900K and market positioning against i7-9700K.

I think the bigger news is that AMD has fully caught up with Intel at IPC.

They were already pretty much caught up in terms of IPC. Only clock speed was lacking.

 

[Darmok N Jalad]

I'm down for a Ryzen9 16 core CPU! AMD, you did it, you have achieved single core performance parity with Intel. Keep the momentum up, and you will win the market.

It's going to be a long 6 months waiting for this, which will be my first AMD system in 12 years.

Oh, and all nice to see AdoredTV being proved right again, despite all the negativity towards him.

Intel hasn’t made any IPC advances since they’ve stalled out at 14nm. I believe that is something they are working toward with their Core replacement. Not to take away from AMD’s achievements here, but Intel is in a pretty big rut, and once they get themselves out of it, I expect them to come out swinging. Hopefully AMD knows this and is not resting for a second.

 

[InVasMani]

The score is very consistent with other reviews, so I don’t believe it’s gimped. Also, I think AMD more wanted to showcase that their demo Ryzen was matching the 9900K, but doing it at 75W vs 125W. It suggests they can not only match Intel in performance, but they have 50W of headroom to move past them. It’s not that far-fetched—Intel is behind on manufacturing, and they are pushing their current node to its absolute limits.

If that is true, then maybe those 5.0ghz rumors are valid. I think Zen was more architecturally limited to the low 4 GHz range than it was node limited. Zen 2 pretty much has to correct that problem so they can advance performance.


Actually, if I remember right, the GPU could just be built right into the IO chip. I believe that’s what happened with the custom GPU ATI built for the Xbox360 and what Intel did with early Core MCM designs. If they shrink that IO+GPU chip to 7nm, it would probably fit the footprint of the base IO chip.

Interesting so they could technically have perhaps two I/O GPU hub chips syncronizing with 2 CPU chiplet's which might utilizing hyper threading between each other for load balancing in perfect tandem with each other or alternating in perfect sync. That way each I/O GPU hub gets it's own CPU L1 cache latency rather than sharing them unapologetic. In fact they could both run in parallel, but alternating the I/O GPU/CPU chips so each chip kind of automatically manages waste heat in a better way in terms of hot spots. Since voltage currents are waves up down on/off staggering them would be ideal for dealing with the heat so make the two CPU dies diagonal from one another and same with GPU I/O dies.

I was actually thinking of Navi a bit in another thread AMD could have a I/O die with 6 chiplets similar to what a Vega 32 would be aka a completely cut in half Vega 64. They'd be better yields naturally and efficiency would be quite a bit better plus the waste heat easier to manage. Basically 6 smaller die Vega chips and one more monolithic I/O die chip sitting between all 6 of them 3 on each side of it. It would be a absolute powerhouse. I mean what does Vega 64 do for traditional ray tracing in terms of frame rates?

Cut that in half and presto no RTX gimmick just pure traditional ray tracing via brute force of essentially a chiplet render farm of sorts. Now with path tracing it could be interesting. We need to get to a point with ray tracing with path tracing though where you can apply that in real time to a scene based on like mipmap/LOD/Culling type behavior selectively for denoise. Simply making the more distant less important and visible scenes have a bit less denoise applied since it's less vital anyway.

Not only this was clearly designed for two dies there's also room for another one TDP wise according to those power figures.

Not that surprised if they shrink that I/O die to 7nm they could squeeze in 3 chiplets alongside it.

Intel hasn’t made any IPC advances since they’ve stalled out at 14nm. I believe that is something they are working toward with their Core replacement. Not to take away from AMD’s achievements here, but Intel is in a pretty big rut, and once they get themselves out of it, I expect them to come out swinging. Hopefully AMD knows this and is not resting for a second.

The gist of it is Intel got really complacent in recent years. I think we'll see something akin to C2D/C2Q transition from AMD64 in response eventually, but that kind of change doesn't happen overnight. Much like AMD64 kicked the pants out of Intel for awhile and like Ryzen is doing pretty well now. I'm just hoping neither company gets to complacent and that they both try to one up the other in tangible significant ways as opposed to oh hey here's a 2-3% performance boost for 100% of the cost of the last generation product lineup enjoy the price gouging.

 

[Melvis]

Good to see this 8core 16 thread CPU beating out the 9900k@4.7GHz in Cinebench and at lower clocks be my guess with that power consumption, 4,6GHz be my guess.

 

[efikkan]

Interesting so they could technically have perhaps two I/O GPU hub chips syncronizing with 2 CPU chiplet's which might utilizing hyper threading between each other for load balancing in perfect tandem with each other or alternating in perfect sync. That way each I/O GPU hub gets it's own CPU L1 cache latency rather than sharing them unapologetic. In fact they could both run in parallel, but alternating the I/O GPU/CPU chips so each chip kind of automatically manages waste heat in a better way in terms of hot spots. Since voltage currents are waves up down on/off staggering them would be ideal for dealing with the heat so make the two CPU dies diagonal from one another and same with GPU I/O dies.

There should be no need for any of this, the IO dies handles queuing of memory accesses from up to 8 chipliets as needed, there should no need for synchronizing threads, as memory accesses are not evenly distributed anyway. L1 and L2 cache are located on the chiplets.

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My concern is that when/if 12/16 core variants arrive, will the dual channel memory controller be enough? Many of the workloads which could utilize this many cores are very bandwidth intensive. I assume Ryzen 3 will use memory beyond DDR4-2933, but to my knowledge only DDR4-3200 is currently finalized by the JEDEC standard. And before anyone suggest overclocking memory, I would remind everyone that it's not a reliable solution.

Anyway, the benchmark conducted on CES was with DDR4-2666.

 

[Captain_Tom]

There should be no need for any of this, the IO dies handles queuing of memory accesses from up to 8 chipliets as needed, there should no need for synchronizing threads, as memory accesses are not evenly distributed anyway. L1 and L2 cache are located on the chiplets.

-----

My concern is that when/if 12/16 core variants arrive, will the dual channel memory controller be enough? Many of the workloads which could utilize this many cores are very bandwidth intensive. I assume Ryzen 3 will use memory beyond DDR4-2933, but to my knowledge only DDR4-3200 is currently finalized by the JEDEC standard. And before anyone suggest overclocking memory, I would remind everyone that it's not a reliable solution.

Anyway, the benchmark conducted on CES was with DDR4-2666.

Exactly. 3200 is still 20% higher than the demo that destroyed the 9900K. It should be plenty for the 12-core 3700X, and after that who cares?

I mean people buying the 16-core models will likely not be buying them for gaming first, and I doubt they will lose any performance. Remember that the 2990WX loses in gaming only because it has "island dies" - it's not because of a lack of bandwidth, it's a lack of a decent connection to bandwidth. And even then, they have shown the 2990WX would perform only ~10% worse in games than the other Ryzen chips if Windows would schedule correctly.

 

[InVasMani]

You could actually fit 3 CPU chiplet's if you rotate one 90 degrees and shift the i/o into the corner. That's w/o needing to even shrink the i/o as well tried it in mspaint out of curiosity. If AMD engineers are savvy enough they could probably re-design such a chip eventually on the same socket w/ or w/o a i/o die shrink. Intel has it's hands full for awhile I guess AMD has a bit of ace or two up it's sleeve.

 

[TheLaughingMan]

Exactly. 3200 is still 20% higher than the demo that destroyed the 9900K. It should be plenty for the 12-core 3700X, and after that who cares?

I mean people buying the 16-core models will likely not be buying them for gaming first, and I doubt they will lose any performance. Remember that the 2990WX loses in gaming only because it has "island dies" - it's not because of a lack of bandwidth, it's a lack of a decent connection to bandwidth. And even then, they have shown the 2990WX would perform only ~10% worse in games than the other Ryzen chips if Windows would schedule correctly.

Actually Level1Tech proved that the issue is definitely the Windows scheduler. It has trouble understanding that the other cores are available all the time and gets itself caught in a loop of moving around threads instead of processing them. I am not sure how much of that is translated to games, but I would have to assume the behavior is the same.

 

[Deleted member 158293]

You could actually fit 3 CPU chiplet's if you rotate one 90 degrees and shift the i/o into the corner. That's w/o needing to even shrink the i/o as well tried it in mspaint out of curiosity. If AMD engineers are savvy enough they could probably re-design such a chip eventually on the same socket w/ or w/o a i/o die shrink. Intel has it's hands full for awhile I guess AMD has a bit of ace or two up it's sleeve.

Yeah, a 24 core Ryzen on AM4 platform would be a very nice, and dense, chip. Competition might bring this out, but IMO not until AMD felt pressure to do so, which right now they surely don't. Also they need income on existing product since their net profit margin is much lower than Intel per unit.

 

[InVasMani]

I'm thinking given it's only dual channel memory and also power/heat for the platform 18c/36t or just 18c/18t could be more likely with a 3 CPU die + 1 I/O die for Ryzen AM4. If it were to happen at all that is. I don't think it's something AMD immediately would be interested in, but they pursue it eventually if they have lot of dies kicking around anyway down the road and want to use them up. I guess it depends on circumstances and how costly it would be to tweak the arrangement of them to make it possible in the first place. It really is quite interesting that 3 of them with the I/O die could still fit snugly together potentially.