AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit

[jmcosta]

I always called the full bulldozer a quad core simply because it was outperformed by a intel quad core with HT, even in many applications that loved multithreading an I5 3570k did.

 

[danbert2000]

I don't think anyone is very surprised by this. AMD could have changed its marketing to 4 cores, SMT+, or 4 FP core, 8 integer core. They didn't because they desperately needed some reason for consumers to buy their crappy CPUs over the reigning Intel 4 core 8 thread champ. By selling "8 cores" they were suggesting that they had twice the processing power of an Intel processor, or at least 50% more since Intel was using HT. The fact that AMD settled means that they were not sure they could win the case. And that's about as close to an admission of guilt than anything else you'll get out of a large company nowadays.

Let's bury the hatchet. AMD clearly figured out SMT with Zen. They took their lumps and now can truthfully say they have many 8 core processors. But there's not much argument any more, the FX line was a lie to try to help AMD limp past their technical disadvantage.

 

[londiste]

i9 9980XE

18C/36T

@ 5200 MHz

525 cb

11687 cb

22x scaling. This one does have SMT but hey, 18 cores are 18 cores. Your time x cores math is a valid expectation, according to you. Cores are cores and everything is set in stone.
Also, you are aware that in your amazing comparison of Piledriver with other CPUs that those newer Intel processors have much more aggressive single core and multi core turbos, right ?

Check this out :

i5 6500

4C/4T

@ 3200 MHz

374 cb

1326 cb

1326 / 374 = 3.54x , 88.5% , interesting. Not quite 100% but much closer to 80% the deficiency goes down to about 6%, noteworthy not noteworthy what do you say. Is this really a quad core I wonder ?

9980XE is 18 cores plus HT. 22.26x - 124%. 24% boost is accurate enough for HT.
i5 6500 runs at 3200MHz all core and 3600MHz single core (12.5% faster). Take that into account and it scales perfectly - 3.99x - effectively 100%.

SMT and similar do increase performance over 100% per core.
Intel HT gives a 25-30% extra, Zen/Zen2 SMT gives 30-35%.
Bulldozer's CMT tends to give 60-65%

And you replying to every comment of mine for the past couple of pages are ... not ... right ?

I don't know. Hoping some meaningful discussion comes out of this somehow?
Or at least we can learn something.

 

[Jism]

Was'nt the opteron 6x00 series based on 2 glued FX or Bulldozer chips? How about those? If there is or was a class action lawsuit, you'd say that they would chase the server area as well?

Really i dont understand the fuss from people. Yes it's a 4 core 8 thread CPU or a different approach to having SMT or some shit. It might not perform as it did but it did it's task. It was sufficient for the most tasks and esp hardcore rendering. Looking at the price point you coud'nt complain either. It was one of the CPU's that allowed them to OC all the way up to 5Ghz ~ 5.2Ghz. They where alot of fun to play with.

These days Intel locks their CPU's and AMD already pushes for max clocks using XFR. There is'nt that much fun in CPU world these days.

 

[seronx]

I have never in my life seen a core being labeled as the block that gets to execute instructions, that's usually simply called the ALU or execution unit. And the control portion gets to fetch and decode the instructions that are fed into the ALU.

The control unit is within the core. Bulldozer's core design is decoupled from the front-end, FPU execution, and the back-end through the L2.

The front-end doesn't decide that thread A can run on core B, vice versa. The cores decide which thread runs on them and its hardlocked.

The scheduler unit, the 40-entry unified scheduler decodes macro-ops from the retire queue which can only be for one thread. Into, micro-ops to be executed within the superscalar datapath, which results can be stored into memory via the data bus.

None of this is controlled by the supposed shared front-end, all of this is handled purely by the core. Of which there are two cores in Bulldozer.

 

[biffzinker]

it was outperformed by a intel quad core with HT

You forgot to mention the out going Phenom II was outperforming the FX as well. When the prior CPU is out scoring the new hotness that's going to get noticed. At the time software wasn't ready for the CMT approach AMD took, some optimization work would of improved the benchmark scores.

Edit: At the time I had a Phenom II x4 960T that unlocked to five cores. I was looking to replace the Phenom II but reviews for the new FX 8150 showed my slight overclock of 3.7 GHz Phenom II x5 was faster.
Later confirmed in some benchmarks I tested. I ended up moving to a Intel Xeon 1240 V2.

 

[londiste]

The control unit is within the core. Bulldozer's core design is decoupled from the front-end, FPU execution, and the back-end through the L2.
The front-end doesn't decide that thread A can run on core B, vice versa. The cores decide which thread runs on them and its hardlocked.
The scheduler unit, the 40-entry unified scheduler decodes macro-ops from the retire queue which can only be for one thread. Into, micro-ops to be executed within the superscalar datapath, which results can be stored into memory via the data bus.
None of this is controlled by the supposed shared front-end, all of this is handled purely by the core. Of which there are two cores in Bulldozer.

https://upload.wikimedia.org/wikipedia/commons/b/b0/AMD_Bulldozer_block_diagram_%28CPU_core_block%29.png

Fetch, decode and dispatch are frontend.

 

[seronx]

Fetch, decode and dispatch are frontend.

Nope, native fetch is done at the retire, native decode/dispatch is done at the scheduler.

 

[londiste]

What are you talking about? Native?
Did you look at the linked diagram?

 

[seronx]

What are you talking about? Native?
Did you look at the linked diagram?

The core in every processor architecture is the one that executes native instructions. Everything else is an heterogeneous accelerator.

Branches don't execute in the front-end, they execute in the cores.
Instructions are fetched and retired by the cores, not the front-end.
etc.

Whether the front-end was VMT2 with absolute competitive sharing or if it was Cluster-based multithreading with no sharing. Would not determine the amount of cores in the module.

 

[londiste]

The core in every processor architecture is the one that executes native instructions. Everything else is an heterogeneous accelerator.

OK, cool. What is the native instruction set for Bulldozer?

Branches don't execute in the front-end, they execute in the cores.
Instructions are fetched and retired by the cores, not the front-end.
etc.

Branches?
Front end is part of core.
Fetch is at the very top of the diagram.
Retire... is not quite what you seem to think it is.

 

[seronx]

OK, cool. What is the native instruction set for Bulldozer?

RISC AMD64, of which control, general-purpose, integer is executed by the cores and FPU is executed in the FPU, etc.

Front end is part of core.

Front-end is an optional unit. It can have seperate designs and it can be totally removed if the application doesn't need to be x86, x86-64 compatible.

FE, L2, FPU => optional units.

 

[londiste]

Interesting.
Tell me, how many cores are there in a Zen CCX?
Also, is FPU a core or not?

 

[seronx]

Tell me, how many cores are there in a Zen CCX?

A single Zen processor has a single core, there eight Zen processors which are eight cores. In a CCX there is four cores, thus four single-core monolithic processors.

However, a single Bulldozer processor has two cores, thus four Bulldozer processors are also eight cores.

Stoney, single dual-core monolithic processors => two cores
Carrizo, two dual-core monolithic processors => four cores
Kaveri, two dual-core monolithic processors => four cores
Trinty, two dual-core monolithic processors => four cores
Orochi, four dual-core monolithic processors => eight cores

 

[londiste]

What defines a processor? A core?
Is there an OS (or software) that can run on RISC AMD64? Can such software be written?

Doesn't monolithic normally refer to a die?

 

[seronx]

What defines a processor? A core?

The industry does... FE/LSU/FPU/L2 doesn't make a core, only the mid_core makes the core.

Is there an OS (or software) that can run on RISC AMD64? Can such software be written?

This is not a concern.

 

[londiste]

Is ALU enough to be a core?

 

[seronx]

Is ALU enough to be a core?

It needs a control unit, instruction bus, data bus as well.

Instruction bus => Retire queue
Control unit => Scheduler
Data bus => Load/store unit
Datapath => EX0/EX1/AGLU0/AGLU1
^-- easily defined a core.

 

[Steevo]

About as smart as the suit against HDD manufacturing difference in data size, raw and formatted, sector size and much else the average consumer doesn't understand twisted by lawyers looking for a paycheck.

 

[londiste]

It needs a control unit, instruction bus, data bus as well.

What functionality does it need in the control unit?
When it comes to buses, it needs access to these and not much more, right?

 

[seronx]

What functionality does it need in the control unit?

The control unit interconnects the ALUs, AGUs, data buses, and manages the execution of instructions. It also executes the branches, thread control if SMT, etc.

When it comes to buses, it needs access to these and not much more, right?

It already has access to all buses in production or else the second core wouldn't work.

 

[Totally]

This post...

…totally called it, especially that last sentence.

AMD could never win this argument without changing over a decade of precedents including by competitors like Sun, ARM, IBM, Intel, and even themselves (Athlon 64 X2). "Integer core" got lost in marketing translation to become something it isn't, a "core." If AMD accurately advertised the product as having "8 integer cores" this lawsuit would have never been filed.

When people don't understand, they are going are to see what they want to see regardless if the proof is right there in front of them. Also if you slice the second image horizontally across and swap the bottom and top then rotate the image 90 degrees it looks an awfully a lot like the first.

 

[Vya Domus]

Is ALU enough to be a core?

While AMD's design is certainly controversial to some, more Interestingly Nvidia is getting much more liberal with these definitions. They reckon that yes, ALUs and FPUs are considered a core, hence their famous CUDA core counts that are in the thousands. We know for sure those can't be seen as a CPU core equivalents at the very least, they are not magicians they can't fit thousands of independent cores on a single die.

The secret sauce is that these are grouped in SMs which subsequently execute instructions , more specifically just one instruction, in groups of 32 because that's the only thing the control unit can do. It can't issue instructions to these cores independently because they can't do the fetch and decode or anything that has to do with control signals on their own. AMD does the same with their GPUs but at the very least they call them by the more generic label of "processors".

If anyone should be crucified for ambiguous and misleading labels, it should be Nvidia.

 

[londiste]

AMD definitely did try calling CUs compute cores when bringing in APUs and HSA initiative.

 

[biffzinker]

understand twisted by lawyers looking for a paycheck.

Who's going to turn down the payout of up to 3.6 million out of the 12.1 million set aside by AMD?