Intel's Alder Lake Processors Could use Foveros 3D Stacking and Feature 16 Cores

[AleksandarK]

Intel is preparing lots of interesting designs for the future and it is slowly shaping their vision for the next generation of computing devices. Following the big.LITTLE design principle of Arm, Intel decided to try and build its version using x86-64 cores instead of Arm ones, called Lakefield. And we already have some information about the new Alder Lake CPUs based on Lakefield design that are set to be released in the future. Thanks to a report from Chrome Unboxed, who found the patches submitted to Chromium open-source browser, used as a base for many browsers like Google Chrome and new Microsoft Edge, there is a piece of potential information that suggests Alder Lake CPUs could arrive very soon.

Rumored to feature up to 16 cores, Alder Lake CPUs could present an x86 iteration of the big.LITTLE design, where one pairs eight "big" and eight "small" cores that are activated according to increased or decreased performance requirements, thus bringing the best of both worlds - power efficiency and performance. This design would be present on Intel's 3D packaging technology called Foveros. The Alder Lake CPU support patch was added on April 27th to the Chrome OS repository, which would indicate that Intel will be pushing these CPUs out relatively quickly. The commit message titled "add support for ADL gpiochip" contained the following: "On Alderlake platform, the pinctrl (gpiochip) driver label is "INTC105x:00", hence declare it properly." The Chrome Unboxed speculates that Alder Lake could come out in mid or late 2021, depending on how fast Intel could supply OEMs with enough volume.


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[ARF]

8 Atom type Gracemont cores and 8 Core type Golden Cove cores, I'm afraid Intel will be lagging behind AMD's Ryzen for many years to come.

 

[Noztra]

Another day, another Intel news about an upcoming CPU line.

How many upcoming CPU’s do they have?

 

[ARF]

Another day, another Intel news about an upcoming CPU line.

How many upcoming CPU’s do they have?

Comet Lake - May 2020
Rocket Lake - Q4 2020
Alder Lake - 2021
Meteor Lake - 2022



The common between them is that none of them has been released so far.

 

[Vayra86]

Of all their options this could get mildly interesting. At least as a PoC and how it will work out in terms of TDP under heavy and light loads.

As an actual product though... seems like far fetched for consumer, and rather desperate too; is Intel saying it is economically feasible to deliver that much extra die space just so its not molten lava? And how about binning? That just got twice as complicated, no? Lots of unanswered questions...

 

[TheoneandonlyMrK]

Of all their options this could get mildly interesting. At least as a PoC and how it will work out in terms of TDP under heavy and light loads.

As an actual product though... seems like far fetched for consumer, and rather desperate too; is Intel saying it is economically feasible to deliver that much extra die space just so its not molten lava? And how about binning? That just got twice as complicated, no? Lots of unanswered questions...

And what node's are we talking, 14nm big cores 10nm little? All 10nm.
Seams like they have a plan n all I'm not sure I like it though.
With big cores done right you can gate most of the cores off on light loads leaving a couple on but with burst processing and race to idle I dunno what is the point ,their competition doesn't need To go anywhere near this as the 4800/4900u show now ,their 5nm parts will be stiff competition.

 

[Mussels]

I hope they dont end up just getting 16 core chips and slapping the failed cores as the 'little' and locking the clocks down low

 

[champsilva]

8 Atom type Gracemont cores and 8 Core type Golden Cove cores, I'm afraid Intel will be lagging behind AMD's Ryzen for many years to come.

Notebook it's intel biggest profit maker (customer side), and this for mobile it's great, imagine low tasks like browsing, office and stuff consuming like 2W, the battery would last longer.

 

[TheoneandonlyMrK]

Notebook it's intel biggest profit maker (customer side), and this for mobile it's great, imagine low tasks like browsing, office and stuff consuming like 2W, the battery would last longer.

True but there are other ways to get there, though 2watts is pure fantasy, your screen at 14/17" is never going to allow that.
Neither is the fact that that version of nothing doesn't happen often ie reading a page.
Watching videos or anything else is also never getting to 2 watts in the next few years.

 

[ARF]

Notebook it's intel biggest profit maker (customer side), and this for mobile it's great, imagine low tasks like browsing, office and stuff consuming like 2W, the battery would last longer.

I don't think so. AMD's Renoir is the best notebook chip ever created.

 

[Ashtr1x]

No idea on this nonsense of Big.Little garbage on Desktop. Look at any ARM processor, the freq will never hold it's clocks due to thermal and power constraints that's why this has been developed. Why do we even need this on an x86 application ? We already have Turbo boost. Esp on Intel the Higher Clocks can be forced on K series CPUs and even on unlocked bins like Mobile Haswell rPGA systems (last of the Socketed CPUs on mobile and actually have an Extreme binned Silicon, 4930MX) so no more SMT, Hyperthreading ? I see this is as a fanless Chip on some macbooks and Project Athena lineup. Not the desktop LGA systems which must outperform their own CML, Ring Bus 5.1GHz ST perf AND Zen3 uArch with their far superior IMCs for higher memory overclocks and super high TDP without any bs power constraints like a crappy BGA smarphone processors. I would be happy to see SMT4 and more of AVX rather than this awful news.

I just hope this is just a garbage rumor and not for the Desktop DIY or HEDT systems. Esp if we talk on the HEDT processors, we know how Intel makes their XCC, HCC and LCC and similarly how AMD bins and makes 4, 8 Chiplet designs and all for maximum profits and scaling across their whole lineup of Silicon prowess and how Desktop systems SKUs are dependent on the same Wafer Lithography tech which are for their Datacenter, primary business.

 

[ARF]

No idea on this nonsense of Big.Little garbage on Desktop. Look at any ARM processor, the freq will never hold it's clocks due to thermal and power constraints that's why this has been developed. Why do we even need this on an x86 application ? We already have Turbo boost. Esp on Intel the Higher Clocks can be forced on K series CPUs and even on unlocked bins like Mobile Haswell rPGA systems (last of the Socketed CPUs on mobile and actually have an Extreme binned Silicon, 4930MX) so no more SMT, Hyperthreading ? I see this is as a fanless Chip on some macbooks and Project Athena lineup. Not the desktop LGA systems which must outperform their own CML, Ring Bus 5.1GHz ST perf AND Zen3 uArch with their far superior IMCs for higher memory overclocks and super high TDP without any bs power constraints like a crappy BGA smarphone processors. I would be happy to see SMT4 and more of AVX rather than this awful news.

I just hope this is just a garbage rumor and not for the Desktop DIY or HEDT systems. Esp if we talk on the HEDT processors, we know how Intel makes their XCC, HCC and LCC and similarly how AMD bins and makes 4, 8 Chiplet designs and all for maximum profits and scaling across their whole lineup of Silicon prowess and how Desktop systems SKUs are dependent on the same Wafer Lithography tech which are for their Datacenter, primary business.

Intel is so desperate because:
1. AMD's Zen is superior;
2. 14nm with pluses;
3. ARM is superior to x86.

I guess BIG.little approach is trying to understand why Apple moves to ARM. And so on.

Intel will have very difficult decade to come.

Any other company in its place would struggle to survive.

 

[chodaboy19]

For non-K or i9 cpus this makes a lot of sense in a total cost of ownership approach.

 

[Turmania]

This is just done to put in as many as cores as possible. It can work not doubting that.

 

[Vayra86]

I hope they dont end up just getting 16 core chips and slapping the failed cores as the 'little' and locking the clocks down low

Ah of course, that answers the binning question

 

[ARF]

This is just done to put in as many as cores as possible. It can work not doubting that.

But, will you be able to use simultaneously both the small and big cores ?

 

[Vayra86]

But, will you be able to use simultaneously both the small and big cores ?

I just couldn't help thinking of this
Needs timestamp Skip to 1:48

 

[ARF]

I just couldn't help thinking of this

Sure but I have asked a serious question and users elsewhere tend to unite around a similar opinion:

Intel Alder Lake-S rumored to feature LGA1700 socket - VideoCardz.com

Intel Rocket Lake-S will give us a taste of what is to come. Alder Lake-S will be a whole new meal. Intel Alder Lake-S A roundup of all Alder Lake-S rumors: Intel Alder Lake-S is a successor to Comet Lake-S. Alder Lake-S will feature a new socket (LGA1700). The socket is expected to support up […]

videocardz.com

 

[Assimilator]

OP:

> Alder Lake CPUs could arrive very soon
> Intel will be pushing these CPUs out relatively quickly

Also OP:

> Alder Lake could come out in mid or late 2021

The last thing does not follow the first two.

 

[Turmania]

But, will you be able to use simultaneously both the small and big cores ?

Probably, say 8 cores boost up to 4.5ghz, and 8 small cores 3ghz or something like that at the same time, dont know about how overclocking will be done though.

 

[Vayra86]

Sure but I have asked a serious question and users elsewhere tend to unite around a similar opinion:

View attachment 153826

Intel Alder Lake-S rumored to feature LGA1700 socket - VideoCardz.com

Intel Rocket Lake-S will give us a taste of what is to come. Alder Lake-S will be a whole new meal. Intel Alder Lake-S A roundup of all Alder Lake-S rumors: Intel Alder Lake-S is a successor to Comet Lake-S. Alder Lake-S will feature a new socket (LGA1700). The socket is expected to support up […]

videocardz.com

Serious answers are not available and its the same sentiment everywhere right? We really don't know anything other than 'it uses Big little'. We can speculate

More cores equals more power used. And from that conclusion... its easy to draw other conclusions. Such as:
1. Windows scheduler and good allocation of workloads will be the key to gaining an advantage over other products
2. Intel's goal must be: faster when its needed (it can turbo high), fall back on little when possible (big cores can cool down and clear TDP budget for a new boost). Any other approach is not feasible, because then they are not competitive against stripped AND full fat performance cores.
4. A new reduction of base clocks on the BIG cores is likely, to clear more TDP headroom for turbo. Or maybe even dial back entirely to idle clock, some 800 mhz, and just have a turbo on top of that. Or maybe fully shut down, but I'm then thinking of latency problems.

So, using the cores at the same time will bring what advantage exactly? I'm not seeing it, do you? For this product to be viable, it needs to be better than either variant of the cores used in it. 8 fast and 8 slow cores are still worse than 16 regular ones at base clock, I reckon...

Interesting stuff indeed What I personally think is that Alder Lake is a way to get 10nm dies out that were planned anyway, and still keep competitive product across the whole stack. Forget 'glued together', Intel is going full scrapyard dive. It also confirms yet again that 10nm scales like shit into performance territory.

 

[champsilva]

True but there are other ways to get there, though 2watts is pure fantasy, your screen at 14/17" is never going to allow that.
Neither is the fact that that version of nothing doesn't happen often ie reading a page.
Watching videos or anything else is also never getting to 2 watts in the next few years.

When i said 2W, was like browsing (and only CPU power consumption)

 

[yeeeeman]

Another day, another Intel news about an upcoming CPU line.

How many upcoming CPU’s do they have?

Well, if you put your mind to work you'll understand why.
But since you didn't I'll tell you.
Intel couldn't fabricate s**t with the 10nm issues. So imagine them having 1,2...n projects aligned, ready for tapeout or in final shape, but with absolutely no posibility of turning them into a product.
Now, that things get a move on, they will pump out all the projects that should've released in the span of the last 4-5 years in two years, till 2022. So that is why you see every day a new product.

For mobile, that is laptops, 2 in 1, tablets and small PCs like NUCs this is going to be a nice product. The power advantage of using a low power core is there, no matter what anyone says.
For highend desktop, these are not ok and hopefully they have something else for that market, otherwise they will continue to lose marketshare.

 

[Tom Yum]

A big.little strategy could work for x86 but the devil will be in the details about how quickly the CPU can transition processes between cores when there is such a performance disparity between the little and big cores. Big.little works as a power saving measure because leakage current scales with transistor numbers, so very large cores have much higher leakage current than smaller cores. This puts a floor in how low processors can drop their power consumption during idle, and this effect gets worse with smaller process nodes. If the presence of small cores allows the processor to completely power down the larger cores during light usage scenarios, then power consumption during light usage will be lower. But, for highly variable loads like gaming, the time it takes to move processes from small to large cores will likely lead to degraded performance and prevent any measurable power saving.

A more sophisticated way would be to allow each core to power off certain elements within the core when not required. For example, powering off a FPU unit when not required, or half the L2 and L3 cache when not needed. But that doesn't allow marketing to scream 'MOAR CORES!' so that option is off the table.

 

[Assimilator]

A more sophisticated way would be to allow each core to power off certain elements within the core when not required. For example, powering off a FPU unit when not required, or half the L2 and L3 cache when not needed. But that doesn't allow marketing to scream 'MOAR CORES!' so that option is off the table.

CPUs have been doing this for over a decade already...