It is a bit weird, but there is a bit of nuance.
All 7nm+ products are on 5nm.
It all started with a codename list on an AMD profile
7nm/6nm/5nm Renoir/Durango/Rembrandt
Renoir is an APU that has launched
Durango is a name of a city like Bixby/Promontory.
Rembrandt is an APU and it is beside the 5nm.
Rembrandt being 5nm, means Zen3 is on 5nm. Hence, everything 7nm+ is actually 5nm.
Because Rembrandt is 5nm, Cezanne being a later model is also 5nm. Cezanne being 5nm means earlier Zen3 parts are also 5nm.
Which lead to this:
7nm Standard Cell Libraries optimized for Low Power, High Performance & High Density - Dolphin Technology
Dolphin Technology provides SoC designers with Standard Cell Libraries optimized for low power, high performance and high density across a broad range of process technologies.www.dolphin-ic.com
- 6-track, Ultra High Density (51nm and 57nm poly pitch)
7nm Standard Cell Libraries optimized for Low Power, High Performance & High Density - Dolphin Technology
Dolphin Technology provides SoC designers with Standard Cell Libraries optimized for low power, high performance and high density across a broad range of process technologies.www.dolphin-ic.com5nm's 57nm poly-pitch might support retapeouts of 7nm+'s 57nm poly pitch.
- 6-track, Ultra High Density (57nm poly pitch)
I believe 7nm+ at Fab 15 is ~10K to ~30K wafer starts currently, there is no demand for it.
While 5nm at Fab 18 in January was 50K wafer starts and March was 80K wafer starts.
We can see literally two fabs running on google maps;
View attachment 169056
Well I really hope you are right as that would be 'epyc'!
I worry that TSMC wouldn't be able to keep up though as the EUV process takes a fair bit longer to complete even though it's simpler with less masking but the power requirements are pretty huge.
Also, this decision will have had to of been made a long time ago because TSMC's 7nm EUV process is not compatible with their 5nm EUV process, so everything will have had to of been designed for 5nm from the start and at that point HiSilicon would have been a massive partner of TSMC and so there wouldn't have been any capacity on 5nm for AMD to use.