Courtlistener is always a stunningly good source on thinks like that!
Bookmark it in case you may run dry on sauce …
Here's the link for the initial complaint filed by VLSI:
→
https://www.courtlistener.com/docket/14917461/1/vlsi-technology-llc-v-intel-corporation/
Of course, due to the nature of the matter of it, it's highly technical and cryptic in layman's terms. Though I take it that it's a solid non-issue for y'all freaks here.
There are essentially 3 patents in question here already. Shamelessly stealing here from
/u/CyberpunkDre (kudos chap!);
Mind you, each claim starts and ends with standard legal jargon but the middle of each has inserts of Intel presentations on the "infringing" technology and how VLSI alleges that the named technology is what is described in the patent.
- First Claim Infringement of U.S. Patent No. 8,156,357
Intel products that use dynamic cache shrink technology in an infringing manner.
Link to the patent in question: → https://patents.google.com/patent/US8156357B2/en
- Second Claim Infringement of U.S. Patent No. 7,523,373
Intel products that use fuses or other non-volatile memory to store information about SRAM minimum voltages in an infringing manner.
Link to the patent in question: → https://patents.google.com/patent/US7523373B2/en
- Third Claim Infringement of U.S. Patent No. 7,725,759
Intel products that use infringing Hardware-Controlled Performance States (“HWP” or “Speed Shift”) technology
Link to the patent in question: → https://patents.google.com/patent/US7725759B2/en
Thank you.
So, basically:
1. Memory size can be controlled by voltage.
Intel designed the Ivy Bridge cache (LLC) in a way that by lowering the voltage to it, less cache was available for use.
2. Related to the one before, but about saving minimum voltage data in non-volatile way.
Intel is saving the minimum voltage for the same cache in SRAM on each Ivy Bridge CPU.
3. Controlling clock speed based on monitoring multiple devices on a bus.
Intel has SpeedShift tech that bases clock speed based on things like core workload.
SpeedShift was added with Skylake and although the complaint does not seem to say that clearly, the infringing part is probably moving that to hardware. Intel had functionally and largely technically similar SpeedStep for a while before that.
By the descriptions in lawsuit the patent system seems pretty broken. Or VLSI is a patent troll in this case.
What is a little suspicious is that the first patent was issued in 2012. Ivy Bridge was launched in that same month.
Second patent is from 2009 and third is from 2010.
Edit:
This makes me curious though, are all the semiconductor companies paying them already or are we waiting for additional lawsuits?
These patents sound simple enough that at least 3rd should be used by pretty much every modern CPU, GPU or *PU really.
Not sure about the first two, maybe nobody does voltage-derived memory sizes but I doubt that is the case.
